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author | Anouk Van Laer <anouk.vanlaer@arm.com> | 2018-10-19 11:19:08 +0100 |
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committer | Anouk Van Laer <anouk.vanlaer@arm.com> | 2018-11-05 09:56:17 +0000 |
commit | 0e9da43cb63cb6876da608bef980d763d58e4381 (patch) | |
tree | 95e4694e4ed812ba1da1025d9a997b004c4624ab /src/arch/arm/tlb.hh | |
parent | fd294813c443fc1e80ed77a76b172d7103cb3fbf (diff) | |
download | gem5-0e9da43cb63cb6876da608bef980d763d58e4381.tar.xz |
arch, arm: Effect of AT instructions on descriptor handling
Some address translation instructions will stop translation after
the 1st stage and intercept the IPA, even in the presence of
stage 2 (eg AT S1E1). However, in the case of a TLB miss, the
table descriptors still need to be translated from IPA to PA to
avoid fetching the wrong addresses. This commit splits whether
IPA->PA translation is required for the VA and/or for the table
descriptors.
Change-Id: Ie53cdc00585f116150256f1d833460931b3bfb7d
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13781
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/tlb.hh')
-rw-r--r-- | src/arch/arm/tlb.hh | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 336b31b78..637240abb 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, 2016 ARM Limited + * Copyright (c) 2010-2013, 2016, 2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -152,6 +152,10 @@ class TLB : public BaseTLB int size; // TLB Size bool isStage2; // Indicates this TLB is part of the second stage MMU bool stage2Req; // Indicates whether a stage 2 lookup is also required + // Indicates whether a stage 2 lookup of the table descriptors is required. + // Certain address translation instructions will intercept the IPA but the + // table descriptors still need to be translated by the stage2. + bool stage2DescReq; uint64_t _attr; // Memory attributes for last accessed TLB entry bool directToStage2; // Indicates whether all translation requests should // be routed directly to the stage 2 TLB |