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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:25 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:25 -0600 |
| commit | 057b451773eb2f6042cf5a1f6d86b39a8a48eff5 (patch) | |
| tree | bcd765a677f68b05b7df4ca272019dda4e9031c0 /src/arch/arm/tlb.hh | |
| parent | a1e82259759ce7290269aeca6742098f1adbf2fd (diff) | |
| download | gem5-057b451773eb2f6042cf5a1f6d86b39a8a48eff5.tar.xz | |
ARM: Add some TLB statistics for ARM
Diffstat (limited to 'src/arch/arm/tlb.hh')
| -rw-r--r-- | src/arch/arm/tlb.hh | 28 |
1 files changed, 20 insertions, 8 deletions
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index bd723e8d1..a6803c415 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -102,14 +102,26 @@ class TLB : public BaseTLB TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false); // Access Stats - mutable Stats::Scalar read_hits; - mutable Stats::Scalar read_misses; - mutable Stats::Scalar read_acv; - mutable Stats::Scalar read_accesses; - mutable Stats::Scalar write_hits; - mutable Stats::Scalar write_misses; - mutable Stats::Scalar write_acv; - mutable Stats::Scalar write_accesses; + mutable Stats::Scalar instHits; + mutable Stats::Scalar instMisses; + mutable Stats::Scalar readHits; + mutable Stats::Scalar readMisses; + mutable Stats::Scalar writeHits; + mutable Stats::Scalar writeMisses; + mutable Stats::Scalar inserts; + mutable Stats::Scalar flushTlb; + mutable Stats::Scalar flushTlbMva; + mutable Stats::Scalar flushTlbMvaAsid; + mutable Stats::Scalar flushTlbAsid; + mutable Stats::Scalar flushedEntries; + mutable Stats::Scalar alignFaults; + mutable Stats::Scalar prefetchFaults; + mutable Stats::Scalar domainFaults; + mutable Stats::Scalar permsFaults; + + Stats::Formula readAccesses; + Stats::Formula writeAccesses; + Stats::Formula instAccesses; Stats::Formula hits; Stats::Formula misses; Stats::Formula accesses; |