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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-25 17:37:06 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-01 15:47:55 +0000 |
| commit | 30746da58f3dbcb37df6214999ad48cb7df1cc4a (patch) | |
| tree | 097ef94a83f7fc0d8bb60aec450b8322f6bee9cc /src/arch/arm/tracers | |
| parent | 312f44831f45c363bb1a97fdc601cb5efc8d5652 (diff) | |
| download | gem5-30746da58f3dbcb37df6214999ad48cb7df1cc4a.tar.xz | |
arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
This patch implements AArch64 Memory Model Feature Register 2
(from ARMv8.2)
Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/13066
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/tracers')
| -rw-r--r-- | src/arch/arm/tracers/tarmac_parser.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc index 68738cba2..67bbb1493 100644 --- a/src/arch/arm/tracers/tarmac_parser.cc +++ b/src/arch/arm/tracers/tarmac_parser.cc @@ -415,6 +415,7 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = { { "id_aa64isar1_el1", MISCREG_ID_AA64ISAR1_EL1 }, { "id_aa64mmfr0_el1", MISCREG_ID_AA64MMFR0_EL1 }, { "id_aa64mmfr1_el1", MISCREG_ID_AA64MMFR1_EL1 }, + { "id_aa64mmfr2_el1", MISCREG_ID_AA64MMFR2_EL1 }, { "ccsidr_el1", MISCREG_CCSIDR_EL1 }, { "clidr_el1", MISCREG_CLIDR_EL1 }, { "aidr_el1", MISCREG_AIDR_EL1 }, |