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| author | Adrian Herrera <adrian.herrera@arm.com> | 2019-11-08 15:25:21 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-18 15:01:01 +0000 |
| commit | 17a0c0b00644c37e9d8539a9de0a02dc213a6834 (patch) | |
| tree | 8ab1d22fcfbc158dafc1a9e92a5d7562c820dc95 /src/arch/arm/tracers | |
| parent | 7e19b26f503435f07dc4b5675061facc521b8c91 (diff) | |
| download | gem5-17a0c0b00644c37e9d8539a9de0a02dc213a6834.tar.xz | |
arch-arm: R/W interface to AArch32 HCR2 misc reg
This patch implements read/write interfaces to HCR2 AArch32 register,
which is mapped to the upper 32 bits of HCR_EL2.
Change-Id: I996023f3ad8233457d19de8a506ebcf106409165
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22832
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/tracers')
| -rw-r--r-- | src/arch/arm/tracers/tarmac_parser.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc index ce2300ed5..1495c7a74 100644 --- a/src/arch/arm/tracers/tarmac_parser.cc +++ b/src/arch/arm/tracers/tarmac_parser.cc @@ -168,6 +168,7 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = { { "hsctlr", MISCREG_HSCTLR }, { "hactlr", MISCREG_HACTLR }, { "hcr", MISCREG_HCR }, + { "hcr2", MISCREG_HCR2 }, { "hdcr", MISCREG_HDCR }, { "hcptr", MISCREG_HCPTR }, { "hstr", MISCREG_HSTR }, |