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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-16 14:20:50 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-20 14:23:19 +0000 |
| commit | 20990ad5e9fc98b1fd5b107e8acad2fa97a4ef75 (patch) | |
| tree | 77e921a9d7ed9402789cb7c4602836f2a5e20d16 /src/arch/arm/utility.cc | |
| parent | e97a1fe390a91f30042d683ebc5e654d39844eda (diff) | |
| download | gem5-20990ad5e9fc98b1fd5b107e8acad2fa97a4ef75.tar.xz | |
arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currEL
Change-Id: I739a9be03ea5caa63540c62fd110eee86a058c4c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20252
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/utility.cc')
| -rw-r--r-- | src/arch/arm/utility.cc | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 73537a89c..924024d0e 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -225,9 +225,7 @@ longDescFormatInUse(ThreadContext *tc) RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc) { - CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); - const ExceptionLevel current_el = - opModeToEL((OperatingMode) (uint8_t) cpsr.mode); + const ExceptionLevel current_el = currEL(tc); const bool is_secure = isSecureBelowEL3(tc); @@ -356,7 +354,7 @@ ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el) bool isBigEndian64(ThreadContext *tc) { - switch (opModeToEL(currOpMode(tc))) { + switch (currEL(tc)) { case EL3: return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee; case EL2: @@ -820,7 +818,7 @@ decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx, bool SPAlignmentCheckEnabled(ThreadContext* tc) { - switch (opModeToEL(currOpMode(tc))) { + switch (currEL(tc)) { case EL3: return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa; case EL2: |