| Age | Commit message (Expand) | Author |
|---|
| 2020-02-01 | arch,sim: Merge initCPU into the ISA System classes. | Gabe Black |
| 2020-02-01 | arch,sim: Merge initCPU and startupCPU. | Gabe Black |
| 2020-01-15 | arch-arm: ELIsInHost, check VHE and SecEL2 | Adrian Herrera |
| 2020-01-15 | arch-arm: Virtualization Host Extensions checking | Adrian Herrera |
| 2019-12-18 | arch-arm: Secure EL2 checking | Adrian Herrera |
| 2019-10-02 | arch-arm: Create helper for sending events (SEV) | Giacomo Travaglini |
| 2019-08-20 | arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currEL | Giacomo Travaglini |
| 2019-08-20 | arch-arm: Replace direct use cpsr.el with currEL helper | Giacomo Travaglini |
| 2019-05-30 | arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s. | Gabe Black |
| 2019-05-23 | arch-arm: Trap virtual accesses to GICv3 SGI registers | Giacomo Travaglini |
| 2019-05-23 | arch-arm: Change mcrMrc15TrapToHyp signature | Giacomo Travaglini |
| 2019-03-14 | arch-arm,cpu: Add initial support for Arm SVE | Giacomo Gabrielli |
| 2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
| 2019-01-25 | cpu, arch, arch-arm: Wire unused VecElem code in the O3 model | Giacomo Travaglini |
| 2019-01-23 | arm: Replace MiscReg with RegVal in utility.(hh|cc). | Gabe Black |
| 2019-01-16 | arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled | Giacomo Travaglini |
| 2018-12-20 | arch, cpu: Remove float type accessors. | Gabe Black |
| 2018-10-26 | arch-arm: Refactor AArch64 MSR/MRS trapping | Giacomo Travaglini |
| 2018-10-26 | arch-arm: Trap to EL2 only if not in Secure State | Giacomo Travaglini |
| 2018-10-26 | arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1 | Giacomo Travaglini |
| 2018-10-01 | arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register | Giacomo Travaglini |
| 2018-06-22 | arch-arm: BadMode checking if corresponding EL is implemented | Giacomo Travaglini |
| 2018-05-29 | arch-arm: MPIDR.MT = 1 in a multithreaded system | Giacomo Travaglini |
| 2018-03-12 | arch-arm: Implement missing aarch32 TLBI registers | Giacomo Travaglini |
| 2018-02-07 | arch-arm: ELUsingAArch32K from armarm pseudocode | Giacomo Travaglini |
| 2018-02-07 | arch-arm: isSecureBelow from armarm pseudocode | Giacomo Travaglini |
| 2018-02-07 | arch-arm: Fix incorrect assumptions in ELIs64 | Chuan Zhu |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2016-08-02 | arm: Fix trapping to Hypervisor during MSR/MRS read/write | Dylan Johnson |
| 2016-08-02 | arm: enable EL2 support | Curtis Dunham |
| 2016-06-02 | arm: Correctly check FP/SIMD access permission in aarch32 | Andreas Sandberg |
| 2016-01-11 | scons: Enable -Wextra by default | Andreas Hansson |
| 2015-09-30 | arm: SMT MPIDR Setting | Mitch Hayenga |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2015-05-26 | arm: Make address translation faster with better caching | Nathanael Premillieu |
| 2014-10-16 | arch: Use shared_ptr for all Faults | Andreas Hansson |
| 2014-04-29 | arm: use condition code registers for ARM ISA | Curtis Dunham |
| 2014-09-03 | arch: Cleanup unused ISA traits constants | Andreas Hansson |
| 2014-05-09 | cpu, arm: Allow the specification of a socket field | Akash Bagdia |
| 2014-03-07 | arm: Fix uninitialised warning with gcc 4.8 | Stephan Diestelhorst |
| 2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers |
| 2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
| 2013-01-07 | arm: Remove the register mapping hack used when copying TCs | Andreas Sandberg |
| 2012-06-05 | cpu: Don't init simple and inorder CPUs if they are defered. | Anthony Gutierrez |
| 2012-03-09 | CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable | Geoffrey Blake |
| 2012-03-09 | ARM: Don't reset CPUs that are going to be switched in. | Ali Saidi |
| 2012-02-24 | MEM: Make port proxies use references rather than pointers | Andreas Hansson |
