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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:20 -0800 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:20 -0800 |
| commit | f6b828d068b046df17b462a4d05af957c038a3a8 (patch) | |
| tree | 1f7be86e41467862c9377e3ca78fa661cc270aed /src/arch/hsail/insts | |
| parent | 2d91e741e8ffc8ae3d40f1e849db87e69af7bfa9 (diff) | |
| download | gem5-f6b828d068b046df17b462a4d05af957c038a3a8.tar.xz | |
style: eliminate explicit boolean comparisons
Result of running 'hg m5style --skip-all --fix-control -a' to get
rid of '== true' comparisons, plus trivial manual edits to get
rid of '== false'/'== False' comparisons.
Left a couple of explicit comparisons in where they didn't seem
unreasonable:
invalid boolean comparison in src/arch/mips/interrupts.cc:155
>> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<<
invalid boolean comparison in src/unittest/unittest.hh:110
>> "EXPECT_FALSE(" #expr ")", (expr) == false)<<
Diffstat (limited to 'src/arch/hsail/insts')
| -rw-r--r-- | src/arch/hsail/insts/decl.hh | 12 | ||||
| -rw-r--r-- | src/arch/hsail/insts/mem.hh | 2 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/hsail/insts/decl.hh b/src/arch/hsail/insts/decl.hh index e2da501b9..90609c365 100644 --- a/src/arch/hsail/insts/decl.hh +++ b/src/arch/hsail/insts/decl.hh @@ -189,7 +189,7 @@ namespace HsailISA int numSrcRegOperands() { int operands = 0; for (int i = 0; i < NumSrcOperands; i++) { - if (src[i].isVectorRegister() == true) { + if (src[i].isVectorRegister()) { operands++; } } @@ -325,13 +325,13 @@ namespace HsailISA int numSrcRegOperands() { int operands = 0; - if (src0.isVectorRegister() == true) { + if (src0.isVectorRegister()) { operands++; } - if (src1.isVectorRegister() == true) { + if (src1.isVectorRegister()) { operands++; } - if (src2.isVectorRegister() == true) { + if (src2.isVectorRegister()) { operands++; } return operands; @@ -485,10 +485,10 @@ namespace HsailISA int numSrcRegOperands() { int operands = 0; - if (src0.isVectorRegister() == true) { + if (src0.isVectorRegister()) { operands++; } - if (src1.isVectorRegister() == true) { + if (src1.isVectorRegister()) { operands++; } return operands; diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh index d3ce76dee..c3b3bd4f9 100644 --- a/src/arch/hsail/insts/mem.hh +++ b/src/arch/hsail/insts/mem.hh @@ -1239,7 +1239,7 @@ namespace HsailISA { int operands = 0; for (int i = 0; i < NumSrcOperands; i++) { - if (src[i].isVectorRegister() == true) { + if (src[i].isVectorRegister()) { operands++; } } |