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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-10 01:21:04 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-10 01:21:04 -0700 |
| commit | 60577eb4caff66a756f260bff6bf3bf8cb7edcba (patch) | |
| tree | 339d0ac0dc4791aed93fad1afe3d1819badcbdb0 /src/arch/mips/isa/operands.isa | |
| parent | 64fe7af51a4cfd01886bf524f4f37d7e1a31fa9f (diff) | |
| download | gem5-60577eb4caff66a756f260bff6bf3bf8cb7edcba.tar.xz | |
ISAs: Get rid of the IControl operand type.
A separate operand type is not necessary to use two bitfields to generate the
index.
Diffstat (limited to 'src/arch/mips/isa/operands.isa')
| -rw-r--r-- | src/arch/mips/isa/operands.isa | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa index 609708a13..c2733be9d 100644 --- a/src/arch/mips/isa/operands.isa +++ b/src/arch/mips/isa/operands.isa @@ -113,10 +113,7 @@ def operands {{ 'Index':('ControlReg','uw','MipsISA::Index',None,1), - #Special cases for when a Control Register Access is dependent on - #a combination of bitfield indices (handles MTCO & MFCO) - # Fixed to allow CP0 Register Offset - 'CP0_RD_SEL': ('IControlReg', 'uw', '(RD << 3 | SEL) + Ctrl_Base_DepTag', None, 1), + 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1), #MT Control Regs 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1), |