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author | Alexandru Dutu <alexandru.dutu@amd.com> | 2014-11-23 18:01:09 -0800 |
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committer | Alexandru Dutu <alexandru.dutu@amd.com> | 2014-11-23 18:01:09 -0800 |
commit | 1f539f13c32ad5a9187d56a098d4c857639b0e05 (patch) | |
tree | 7618c3b946d9c25d9b22018f226eee77b6de4aaf /src/arch/mips | |
parent | c11bcb8119273ef91c40a25b8fd9471a887d0ee5 (diff) | |
download | gem5-1f539f13c32ad5a9187d56a098d4c857639b0e05.tar.xz |
mem: Page Table map api modification
This patch adds uncacheable/cacheable and read-only/read-write attributes to
the map method of PageTableBase. It also modifies the constructor of TlbEntry
structs for all architectures to consider the new attributes.
Diffstat (limited to 'src/arch/mips')
-rwxr-xr-x | src/arch/mips/pagetable.hh | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh index 8678eb7e4..992d6649b 100755 --- a/src/arch/mips/pagetable.hh +++ b/src/arch/mips/pagetable.hh @@ -83,7 +83,14 @@ struct TlbEntry { Addr _pageStart; TlbEntry() {} - TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {} + TlbEntry(Addr asn, Addr vaddr, Addr paddr, + bool uncacheable, bool read_only) + : _pageStart(paddr) + { + if (uncacheable || read_only) + warn("MIPS TlbEntry does not support uncacheable" + " or read-only mappings\n"); + } Addr pageStart() { |