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| author | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2018-10-16 16:04:08 +0100 |
|---|---|---|
| committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-01-30 16:57:54 +0000 |
| commit | 25474167e5b247d1b91fbf802c5b396a63ae705e (patch) | |
| tree | b509597b23d792734f55c33b8125eebfbd9cd3a5 /src/arch/mips | |
| parent | c6f5db8743f19b02a38146d9cf2a829883387008 (diff) | |
| download | gem5-25474167e5b247d1b91fbf802c5b396a63ae705e.tar.xz | |
arch,cpu: Add vector predicate registers
Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.
Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/mips')
| -rw-r--r-- | src/arch/mips/isa.hh | 6 | ||||
| -rw-r--r-- | src/arch/mips/registers.hh | 27 |
2 files changed, 25 insertions, 8 deletions
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh index ffcb3f1dc..cea2d5412 100644 --- a/src/arch/mips/isa.hh +++ b/src/arch/mips/isa.hh @@ -165,6 +165,12 @@ namespace MipsISA return reg; } + int + flattenVecPredIndex(int reg) const + { + return reg; + } + // dummy int flattenCCIndex(int reg) const diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh index 6f7097b08..633199c94 100644 --- a/src/arch/mips/registers.hh +++ b/src/arch/mips/registers.hh @@ -32,6 +32,7 @@ #ifndef __ARCH_MIPS_REGISTERS_HH__ #define __ARCH_MIPS_REGISTERS_HH__ +#include "arch/generic/vec_pred_reg.hh" #include "arch/generic/vec_reg.hh" #include "arch/mips/generated/max_inst_regs.hh" #include "base/logging.hh" @@ -55,6 +56,10 @@ const int NumFloatSpecialRegs = 5; const int MaxShadowRegSets = 16; // Maximum number of shadow register sets const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// +const int NumVecRegs = 1; // Not applicable to MIPS + // (1 to prevent warnings) +const int NumVecPredRegs = 1; // Not applicable to MIPS + // (1 to prevent warnings) const int NumCCRegs = 0; const uint32_t MIPS32_QNAN = 0x7fbfffff; @@ -289,14 +294,20 @@ typedef RegVal MiscReg; // dummy typedef since we don't have CC regs typedef uint8_t CCReg; -// dummy typedefs since we don't have vector regs -constexpr unsigned NumVecElemPerVecReg = 2; -using VecElem = uint32_t; -using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; -using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; -using VecRegContainer = VecReg::Container; -// This has to be one to prevent warnings that are treated as errors -constexpr unsigned NumVecRegs = 1; +// Not applicable to MIPS +using VecElem = ::DummyVecElem; +using VecReg = ::DummyVecReg; +using ConstVecReg = ::DummyConstVecReg; +using VecRegContainer = ::DummyVecRegContainer; +constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; +constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes; + +// Not applicable to MIPS +using VecPredReg = ::DummyVecPredReg; +using ConstVecPredReg = ::DummyConstVecPredReg; +using VecPredRegContainer = ::DummyVecPredRegContainer; +constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits; +constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; } // namespace MipsISA |