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path: root/src/arch/mips
AgeCommit message (Expand)Author
2020-02-01arch,sim: Merge initCPU into the ISA System classes.Gabe Black
2020-02-01arch,sim: Merge initCPU and startupCPU.Gabe Black
2020-01-22arch: Get rid of the unused (and mostly undefined) zeroRegisters.Gabe Black
2019-12-10sim,arch: Collapse the ISA specific versions of m5Syscall.Gabe Black
2019-12-10arch,cpu,sim: Push syscall number determination up to processes.Gabe Black
2019-12-10arch: Get rid of the now unused setSyscallArg.Gabe Black
2019-12-10arch: Stop using setSyscallArg to set argc and argv.Gabe Black
2019-11-18arch: Get rid of the (Big|Little)EndianGuest namespaces.Gabe Black
2019-11-18arch: Make and use endian specific versions of the mem helpers.Gabe Black
2019-11-07mips: Replace gtoh and htog with letoh and htole.Gabe Black
2019-11-02arch,cpu: Move endianness conversion of inst bytes into the ISA.Gabe Black
2019-10-30arch,sim: Make copyStringArray take an explicit endianness.Gabe Black
2019-10-30arch: Make endianness a property of the OS class syscalls can consume.Gabe Black
2019-10-25mips,riscv: Get rid of some Alpha cruft in these System classes.Gabe Black
2019-10-25cpu: Create a PCEventScope class to abstract the scope of PCEvents.Gabe Black
2019-10-19arch: Make a base class for Interrupts.Gabe Black
2019-10-16arch,base,sim: Move Process loader hooks into the Process class.Gabe Black
2019-10-12arch,base: Separate the idea of a memory image and object file.Gabe Black
2019-10-10arch,base: Stop loading the interpreter in ElfObject.Gabe Black
2019-10-10arch, base: Stop assuming object files have three segments.Gabe Black
2019-10-09arch-mips,arch-riscv,base: Get rid of the unused HexFile class.Gabe Black
2019-10-09base: Rename Section to Segment, and some of its members.Gabe Black
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
2019-05-30arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.Gabe Black
2019-05-30arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.Gabe Black
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
2019-05-21sim-se: change syscall function signatureBrandon Potter
2019-05-20mips: Add an object file loader for linux.Gabe Black
2019-04-30arch: Stop using TheISA within the ISAs.Gabe Black
2019-04-29mips: Implement readRegOtherThread and setRegOtherThread directly.Gabe Black
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
2019-04-03misc: Removed inconsistency in O3* debug msgsAndrea Mondelli
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-12arch-mips: Remove unused Python fileAndreas Sandberg
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
2019-01-31mips: Stop using architecture specific register types.Gabe Black
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-24base: arch: Get rid of the now unused FloatRegVal type.Gabe Black
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
2019-01-16arch: Make the ISA register types aliases for the global types.Gabe Black
2018-12-20arch, cpu: Remove float type accessors.Gabe Black
2018-11-27arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.Gabe Black
2018-11-06mips: Change the integer and fp register widths to be 64 bits.Gabe Black
2018-11-06mips: Clean up type overrides for operands.Gabe Black
2018-11-06mips: Explicitly truncate the syscall return value down to 32 bits.Gabe Black
2018-10-17arch: Get rid of the unused type AnyReg.Gabe Black