diff options
| author | Gabe Black <gabeblack@google.com> | 2019-09-02 21:26:12 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-10-19 01:45:48 +0000 |
| commit | ae390c629f2a10fd6a1c2eb50b7d3510d6e091da (patch) | |
| tree | 51f12635838755ef7519bea1c72bfb96e0214336 /src/arch/mips | |
| parent | 1c047f8b92f5708bbef50d24cf47902d5da313e3 (diff) | |
| download | gem5-ae390c629f2a10fd6a1c2eb50b7d3510d6e091da.tar.xz | |
arch: Make a base class for Interrupts.
That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.
Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/mips')
| -rw-r--r-- | src/arch/mips/MipsInterrupts.py | 4 | ||||
| -rw-r--r-- | src/arch/mips/interrupts.cc | 2 | ||||
| -rw-r--r-- | src/arch/mips/interrupts.hh | 8 |
3 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/mips/MipsInterrupts.py b/src/arch/mips/MipsInterrupts.py index 9cde5daef..106570171 100644 --- a/src/arch/mips/MipsInterrupts.py +++ b/src/arch/mips/MipsInterrupts.py @@ -26,9 +26,9 @@ # # Authors: Gabe Black -from m5.SimObject import SimObject +from m5.objects.BaseInterrupts import BaseInterrupts -class MipsInterrupts(SimObject): +class MipsInterrupts(BaseInterrupts): type = 'MipsInterrupts' cxx_class = 'MipsISA::Interrupts' cxx_header = 'arch/mips/interrupts.hh' diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc index a8c94169d..94d0535ca 100644 --- a/src/arch/mips/interrupts.cc +++ b/src/arch/mips/interrupts.cc @@ -153,7 +153,7 @@ Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const } void -Interrupts::updateIntrInfo(ThreadContext *tc) const +Interrupts::updateIntrInfo(ThreadContext *tc) { //Nothing needs to be done. } diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh index ce9e0e4a3..02927ef2a 100644 --- a/src/arch/mips/interrupts.hh +++ b/src/arch/mips/interrupts.hh @@ -33,12 +33,12 @@ #include <string> +#include "arch/generic/interrupts.hh" #include "arch/mips/faults.hh" #include "base/compiler.hh" #include "base/logging.hh" #include "params/MipsInterrupts.hh" #include "sim/serialize.hh" -#include "sim/sim_object.hh" class BaseCPU; class Checkpoint; @@ -46,7 +46,7 @@ class Checkpoint; namespace MipsISA { -class Interrupts : public SimObject +class Interrupts : public BaseInterrupts { public: typedef MipsInterruptsParams Params; @@ -57,7 +57,7 @@ class Interrupts : public SimObject return dynamic_cast<const Params *>(_params); } - Interrupts(Params * p) : SimObject(p) + Interrupts(Params * p) : BaseInterrupts(p) { } @@ -104,7 +104,7 @@ class Interrupts : public SimObject // MIPS cause register with the instatus variable. instatus // is essentially a copy of the MIPS cause[IP7:IP0] // - void updateIntrInfo(ThreadContext *tc) const; + void updateIntrInfo(ThreadContext *tc); bool interruptsPending(ThreadContext *tc) const; bool onCpuTimerInterrupt(ThreadContext *tc) const; bool checkInterrupts(ThreadContext *tc) const; |