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authorAlec Roelke <ar4jc@virginia.edu>2017-11-07 14:15:41 -0500
committerAlec Roelke <ar4jc@virginia.edu>2017-11-29 00:55:46 +0000
commiteb02066b31c85d22c67d1ead61048c196653ba1f (patch)
tree1ab43820091dcf702bf2e7ed083eb27bd3cfb313 /src/arch/riscv/isa/includes.isa
parentd3ecb5d406a3dc12c53a20c271db3027b8477c39 (diff)
downloadgem5-eb02066b31c85d22c67d1ead61048c196653ba1f.tar.xz
arch-riscv: Move standard ops out of ISA
This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/isa/includes.isa')
-rw-r--r--src/arch/riscv/isa/includes.isa1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa
index 48f2b1957..dfd0f37b4 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -42,6 +42,7 @@ output header {{
#include <tuple>
#include <vector>
+#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"