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| author | Gabe Black <gabeblack@google.com> | 2018-11-21 16:20:57 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-02-01 01:22:19 +0000 |
| commit | a119a963240a35ab66a5baee3f77cfcd99c6bbbb (patch) | |
| tree | c883d37ed479e92c23d881a48b8f2abec469faf7 /src/arch/riscv | |
| parent | fbdf0b689eb31543292f52c71d14152d8ff1156a (diff) | |
| download | gem5-a119a963240a35ab66a5baee3f77cfcd99c6bbbb.tar.xz | |
cpu, arch: Replace the CCReg type with RegVal.
Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.
Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/registers.hh | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index e2d1d154b..c2e1fd2b5 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -64,8 +64,6 @@ using RiscvISAInst::MaxInstSrcRegs; using RiscvISAInst::MaxInstDestRegs; const int MaxMiscDestRegs = 1; -typedef uint8_t CCReg; // Not applicable to Riscv - // Not applicable to RISC-V using VecElem = ::DummyVecElem; using VecReg = ::DummyVecReg; |