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author | Gabe Black <gblack@eecs.umich.edu> | 2007-01-24 19:57:36 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-01-24 19:57:36 -0500 |
commit | 5f50dfa5d037e56e73c68f4c087491f57b52f677 (patch) | |
tree | cf70c6b765bafeb489a07bd688053e0b180c6cf0 /src/arch/sparc/faults.cc | |
parent | b8fc86e28f15b03ba82465b2a1dcf0725c769bad (diff) | |
parent | 4301e4cd08018eb56b4f196afcce9a8311f390b4 (diff) | |
download | gem5-5f50dfa5d037e56e73c68f4c087491f57b52f677.tar.xz |
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision : 2d7ae62a59b91d735bbac093f8a4ab542ea75eee
Diffstat (limited to 'src/arch/sparc/faults.cc')
-rw-r--r-- | src/arch/sparc/faults.cc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index d94c05a0f..a6f4343ae 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -314,6 +314,11 @@ void doREDFault(ThreadContext *tc, TrapType tt) TL++; + if (bits(PSTATE, 3,3)) { + PC &= mask(32); + NPC &= mask(32); + } + //set TSTATE.gl to gl replaceBits(TSTATE, 42, 40, GL); //set TSTATE.ccr to ccr @@ -394,6 +399,11 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) MiscReg PC = tc->readPC(); MiscReg NPC = tc->readNextPC(); + if (bits(PSTATE, 3,3)) { + PC &= mask(32); + NPC &= mask(32); + } + //Increment the trap level TL++; tc->setMiscReg(MISCREG_TL, TL); |