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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-12-08 00:27:43 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-12-08 00:27:43 -0800 |
| commit | f01d2efe8a106692fd83936d3c6d3565a001616c (patch) | |
| tree | f1afbc4091f83a03cf3fd566927d36e9ed88cfd2 /src/arch/sparc/isa/operands.isa | |
| parent | d3e021820eb9916d63b96ba732ccc0783626433b (diff) | |
| download | gem5-f01d2efe8a106692fd83936d3c6d3565a001616c.tar.xz | |
SPARC: Take advantage of new PCState syntax.
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index a72fd12b9..dfc71f419 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -129,7 +129,9 @@ def operands {{ #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12), 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12), - 'PCS': ('PCState', 'udw', None, (None, None, 'IsControl'), 30), + 'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30), + 'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30), + 'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30), # Registers which are used explicitly in instructions 'R0': ('IntReg', 'udw', '0', None, 6), 'R1': ('IntReg', 'udw', '1', None, 7), |