Merge zizzer.eecs.umich.edu:/bk/newmem

into  ewok.(none):/home/gblack/m5/newmemo3

src/sim/byteswap.hh:
    Hand Merge

--HG--
extra : convert_revision : 640d33ad0c416934e8a5107768e7f1dce6709ca8

2 files changed, 25 insertions, 11 deletions

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 8abaf1007..e59ce9d11 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -190,7 +190,7 @@ decode OP default Unknown::unknown()
             }});
             0x0B: smul({{
                 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
-                Y = Rd.sdw;
+                Y = Rd.sdw<63:32>;
             }});
             0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
             0x0D: udivx({{
@@ -471,12 +471,12 @@ decode OP default Unknown::unknown()
                 //0x11-0x1F should cause an illegal instruction exception
             }
             0x2B: BasicOperate::flushw({{
-                if(NWindows - 2 - Cansave == 0)
+                if(NWindows - 2 - Cansave != 0)
                 {
                     if(Otherwin)
-                        fault = new SpillNOther(Wstate<5:3>);
+                        fault = new SpillNOther(4*Wstate<5:3>);
                     else
-                        fault = new SpillNNormal(Wstate<2:0>);
+                        fault = new SpillNNormal(4*Wstate<2:0>);
                 }
             }});
             0x2C: decode MOVCC3
@@ -891,9 +891,9 @@ decode OP default Unknown::unknown()
                     if(Canrestore == 0)
                     {
                         if(Otherwin)
-                            fault = new FillNOther(Wstate<5:3>);
+                            fault = new FillNOther(4*Wstate<5:3>);
                         else
-                            fault = new FillNNormal(Wstate<2:0>);
+                            fault = new FillNNormal(4*Wstate<2:0>);
                     }
                     //Check for alignment faults
                     else if(target & 0x3)
@@ -941,9 +941,9 @@ decode OP default Unknown::unknown()
                 if(Cansave == 0)
                 {
                     if(Otherwin)
-                        fault = new SpillNOther(Wstate<5:3>);
+                        fault = new SpillNOther(4*Wstate<5:3>);
                     else
-                        fault = new SpillNNormal(Wstate<2:0>);
+                        fault = new SpillNNormal(4*Wstate<2:0>);
                 }
                 else if(Cleanwin - Canrestore == 0)
                 {
@@ -961,9 +961,9 @@ decode OP default Unknown::unknown()
                 if(Canrestore == 0)
                 {
                     if(Otherwin)
-                        fault = new FillNOther(Wstate<5:3>);
+                        fault = new FillNOther(4*Wstate<5:3>);
                     else
-                        fault = new FillNNormal(Wstate<2:0>);
+                        fault = new FillNNormal(4*Wstate<2:0>);
                 }
                 else
                 {
@@ -1040,6 +1040,12 @@ decode OP default Unknown::unknown()
             0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
             0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
             0x13: decode EXT_ASI {
+                //ASI_LDTD_AIUP
+                0x22: TwinLoad::ldtx_aiup(
+                    {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+                //ASI_LDTD_AIUS
+                0x23: TwinLoad::ldtx_aius(
+                    {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
                 //ASI_QUAD_LDD
                 0x24: TwinLoad::ldtx_quad_ldd(
                     {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
@@ -1058,6 +1064,12 @@ decode OP default Unknown::unknown()
                 //ASI_LDTX_N_L
                 0x2F: TwinLoad::ldtx_n_l(
                     {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+                //ASI_LDTX_P
+                0xE2: TwinLoad::ldtx_p(
+                    {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+                //ASI_LDTX_S
+                0xE3: TwinLoad::ldtx_s(
+                    {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
                 default: ldtwa({{
                         uint64_t val = Mem.udw;
                         RdLow = val<31:0>;
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 62ac4b43a..352e963b3 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -451,6 +451,8 @@ let {{
             flag_code = ''
             if (microPc == 7):
                 flag_code = "flags[IsLastMicroOp] = true;"
+            elif (microPc == 0):
+                flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
             else:
                 flag_code = "flags[IsDelayedCommit] = true;"
             pcedCode = matcher.sub("Frd_%d" % microPc, code)
@@ -492,7 +494,7 @@ let {{
                 flag_code = "flags[IsLastMicroOp] = true;"
                 pcedCode = matcher.sub("RdHigh", code)
             else:
-                flag_code = "flags[IsDelayedCommit] = true;"
+                flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
                 pcedCode = matcher.sub("RdLow", code)
             iop = InstObjParams(name, Name, 'TwinMem',
                     {"code": pcedCode, "ea_code": addrCalcReg,