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| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2014-08-26 10:13:23 -0400 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2014-08-26 10:13:23 -0400 |
| commit | a3d3eb0ff777e0580aa30f52f31958a090cbe3af (patch) | |
| tree | 0827b8360c703fa9cba3ec29bb85558459d45405 /src/arch/sparc/miscregs.hh | |
| parent | 3efabb4b2f59526e35b647aa16ffc1124e002924 (diff) | |
| download | gem5-a3d3eb0ff777e0580aa30f52f31958a090cbe3af.tar.xz | |
sparc: Fixup bit ordering in the PSTATE bit union
The order of the MSB and LSB bit of the mm field in the PSTATE union
is wrong. Any access to this field will currently be ignored and reads
will always return zero. This patch fixes the ordering so it is <MSB,
LSB> instead of <LSB, MSB>.
Diffstat (limited to 'src/arch/sparc/miscregs.hh')
| -rw-r--r-- | src/arch/sparc/miscregs.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/sparc/miscregs.hh b/src/arch/sparc/miscregs.hh index b55fb7d44..6c5118f8a 100644 --- a/src/arch/sparc/miscregs.hh +++ b/src/arch/sparc/miscregs.hh @@ -129,7 +129,7 @@ BitUnion16(PSTATE) Bitfield<2> priv; Bitfield<3> am; Bitfield<4> pef; - Bitfield<6, 7> mm; + Bitfield<7, 6> mm; Bitfield<8> tle; Bitfield<9> cle; Bitfield<10> pid0; |