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| author | Gabe Black <gabeblack@google.com> | 2018-10-18 17:50:42 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-22 21:16:10 +0000 |
| commit | 1ab1500dfd0cb64b2fef7fb5e0f9e1fa007d2481 (patch) | |
| tree | e2c9cbab3738a79463e6ad9defbe845efb764a51 /src/arch/sparc/ua2005.cc | |
| parent | 230b892fa3f484a46f4cd77f889f8793416b91e2 (diff) | |
| download | gem5-1ab1500dfd0cb64b2fef7fb5e0f9e1fa007d2481.tar.xz | |
sparc: Get rid of some register type definitions.
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been
supplanted by the global types RegVal and FloatRegVal.
Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44
Reviewed-on: https://gem5-review.googlesource.com/c/13627
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/sparc/ua2005.cc')
| -rw-r--r-- | src/arch/sparc/ua2005.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 1a248d342..4cafff47c 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -88,7 +88,7 @@ getMiscRegName(RegIndex index) } void -ISA::setFSReg(int miscReg, MiscReg val, ThreadContext *tc) +ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -242,7 +242,7 @@ ISA::setFSReg(int miscReg, MiscReg val, ThreadContext *tc) } } -MiscReg +RegVal ISA::readFSReg(int miscReg, ThreadContext * tc) { uint64_t temp; |