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| author | Gabe Black <gblack@eecs.umich.edu> | 2012-02-11 14:16:38 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-02-11 14:16:38 -0800 |
| commit | 5b557a314f4dbde6f029b3f75c211332ac360f3a (patch) | |
| tree | 8be804d79afc881903830e5281fc86b7f7d5d5dc /src/arch/sparc/ua2005.cc | |
| parent | aa513a4a99cb8dfc6b605797acbbb64a5601ab6e (diff) | |
| download | gem5-5b557a314f4dbde6f029b3f75c211332ac360f3a.tar.xz | |
SPARC: Make PSTATE and HPSTATE a BitUnion.
This gets rid of cryptic bits of code with lots of bit manipulation, and makes
some comments redundant.
Diffstat (limited to 'src/arch/sparc/ua2005.cc')
| -rw-r--r-- | src/arch/sparc/ua2005.cc | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index e6ab64de9..5948e0713 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -206,13 +206,18 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_HPSTATE: - // T1000 spec says impl. dependent val must always be 1 - setMiscRegNoEffect(miscReg, val | HPSTATE::id); - if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) - cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); - else - cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); - break; + { + HPSTATE newVal = val; + newVal.id = 1; + // T1000 spec says impl. dependent val must always be 1 + setMiscRegNoEffect(miscReg, newVal); + newVal = hpstate; + if (newVal.tlz && tl == 0 && !newVal.hpriv) + cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); + else + cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); + break; + } case MISCREG_HTSTATE: setMiscRegNoEffect(miscReg, val); break; |