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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 15:04:31 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 15:04:31 -0500 |
commit | 689cab36c90b56b3c8a7cda16d758acdd89f9de1 (patch) | |
tree | 2f0115320e0a6cfd13e5b054baa0ca13d5655519 /src/arch/sparc/vtophys.cc | |
parent | 329db76e47c825d4ecbe0f5251dbcfaf2ec09516 (diff) | |
download | gem5-689cab36c90b56b3c8a7cda16d758acdd89f9de1.tar.xz |
*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
Diffstat (limited to 'src/arch/sparc/vtophys.cc')
-rw-r--r-- | src/arch/sparc/vtophys.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc index cb545185a..9a93950d2 100644 --- a/src/arch/sparc/vtophys.cc +++ b/src/arch/sparc/vtophys.cc @@ -66,7 +66,7 @@ namespace SparcISA // 4. We are not priv, use ctxN0* tsbs to find the page // For all accesses we check the tlbs first since it's possible that // long standing pages (e.g. locked kernel mappings) won't be in the tsb - uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); + uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); bool hpriv = bits(tlbdata,0,0); //bool priv = bits(tlbdata,2,2); |