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| author | Gabe Black <gabeblack@google.com> | 2018-10-18 17:34:08 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-22 21:15:45 +0000 |
| commit | 230b892fa3f484a46f4cd77f889f8793416b91e2 (patch) | |
| tree | 53b32ed7120d019399e36d04655487745bbba9ee /src/arch/sparc | |
| parent | 774770a6410abb129e2a19de1ca50d7c0c311fef (diff) | |
| download | gem5-230b892fa3f484a46f4cd77f889f8793416b91e2.tar.xz | |
arch: cpu: Stop passing around misc registers by reference.
These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.
Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/sparc')
| -rw-r--r-- | src/arch/sparc/isa.hh | 7 | ||||
| -rw-r--r-- | src/arch/sparc/ua2005.cc | 2 |
2 files changed, 4 insertions, 5 deletions
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index 82fee0d00..9209ba3de 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -116,7 +116,7 @@ class ISA : public SimObject // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu - void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc); + void setFSReg(int miscReg, MiscReg val, ThreadContext *tc); MiscReg readFSReg(int miscReg, ThreadContext * tc); // Update interrupt state on softint or pil change @@ -186,9 +186,8 @@ class ISA : public SimObject MiscReg readMiscRegNoEffect(int miscReg) const; MiscReg readMiscReg(int miscReg, ThreadContext *tc); - void setMiscRegNoEffect(int miscReg, const MiscReg val); - void setMiscReg(int miscReg, const MiscReg val, - ThreadContext *tc); + void setMiscRegNoEffect(int miscReg, MiscReg val); + void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc); RegId flattenRegId(const RegId& regId) const diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index d8af29b91..1a248d342 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -88,7 +88,7 @@ getMiscRegName(RegIndex index) } void -ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) +ISA::setFSReg(int miscReg, MiscReg val, ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); |