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path: root/src/arch/sparc
AgeCommit message (Expand)Author
2020-02-01arch,sim: Merge initCPU into the ISA System classes.Gabe Black
2020-02-01arch,sim: Merge initCPU and startupCPU.Gabe Black
2020-01-22arch: Get rid of the unused (and mostly undefined) zeroRegisters.Gabe Black
2019-12-10sim,arch: Collapse the ISA specific versions of m5Syscall.Gabe Black
2019-12-10arch,cpu,sim: Push syscall number determination up to processes.Gabe Black
2019-12-10arch: Get rid of the now unused setSyscallArg.Gabe Black
2019-12-04sparc: Fix the getresuidFunc prototype.Gabe Black
2019-12-04sparc: Fix the predecoder's moreBytes method.Gabe Black
2019-11-18arch: Get rid of the (Big|Little)EndianGuest namespaces.Gabe Black
2019-11-18arch: Make and use endian specific versions of the mem helpers.Gabe Black
2019-11-07sparc: Replace htog and gtoh with htobe and betoh.Gabe Black
2019-11-02arch,cpu: Move endianness conversion of inst bytes into the ISA.Gabe Black
2019-10-30arch,sim: Make copyStringArray take an explicit endianness.Gabe Black
2019-10-30arch: Make endianness a property of the OS class syscalls can consume.Gabe Black
2019-10-30sparc: Create a helper functions to install firmware images.Gabe Black
2019-10-19arch: Make a base class for Interrupts.Gabe Black
2019-10-16arch,base,sim: Move Process loader hooks into the Process class.Gabe Black
2019-10-12arch,base: Separate the idea of a memory image and object file.Gabe Black
2019-10-10arch,base: Stop loading the interpreter in ElfObject.Gabe Black
2019-10-10arch, base: Stop assuming object files have three segments.Gabe Black
2019-10-09base: Rename Section to Segment, and some of its members.Gabe Black
2019-09-13sparc: Fix a warning/error in tlb.cc.Gabe Black
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
2019-05-30arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.Gabe Black
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
2019-05-21sim-se: change syscall function signatureBrandon Potter
2019-05-20sparc: Add an object file loader for linux and solaris.Gabe Black
2019-04-30arch: Stop using TheISA within the ISAs.Gabe Black
2019-04-30sparc: Move translation constants from isa_traits.hh into tlb.hh.Gabe Black
2019-04-30sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.Gabe Black
2019-04-30arch: Remove the mt.hh switching header.Gabe Black
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-22sparc: Get rid of some register type definitions.Gabe Black
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
2019-01-16arch: Make the ISA register types aliases for the global types.Gabe Black
2019-01-10sim-se: Refactor clone to avoid most ifdefsAndreas Sandberg
2018-11-05sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.Gabe Black
2018-10-17arch: Get rid of the unused type AnyReg.Gabe Black
2018-10-12sparc: Use big endian packet accessors.Gabe Black
2018-09-19syscall_emul: expand AuxVector classBrandon Potter
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-03-27sparc: Add some missing M5_FALLTHROUGHs and breaks.Gabe Black
2018-03-26arch: Fix all override related warnings.Gabe Black
2018-03-26arch: Add a virtual asBytes function to the StaticInst class.Gabe Black