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| author | Gabe Black <gabeblack@google.com> | 2019-09-02 21:26:12 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-10-19 01:45:48 +0000 |
| commit | ae390c629f2a10fd6a1c2eb50b7d3510d6e091da (patch) | |
| tree | 51f12635838755ef7519bea1c72bfb96e0214336 /src/arch/sparc | |
| parent | 1c047f8b92f5708bbef50d24cf47902d5da313e3 (diff) | |
| download | gem5-ae390c629f2a10fd6a1c2eb50b7d3510d6e091da.tar.xz | |
arch: Make a base class for Interrupts.
That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.
Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/sparc')
| -rw-r--r-- | src/arch/sparc/SparcInterrupts.py | 4 | ||||
| -rw-r--r-- | src/arch/sparc/interrupts.hh | 5 | ||||
| -rw-r--r-- | src/arch/sparc/isa.cc | 1 |
3 files changed, 6 insertions, 4 deletions
diff --git a/src/arch/sparc/SparcInterrupts.py b/src/arch/sparc/SparcInterrupts.py index c11176164..04979ad09 100644 --- a/src/arch/sparc/SparcInterrupts.py +++ b/src/arch/sparc/SparcInterrupts.py @@ -26,9 +26,9 @@ # # Authors: Gabe Black -from m5.SimObject import SimObject +from m5.objects.BaseInterrupts import BaseInterrupts -class SparcInterrupts(SimObject): +class SparcInterrupts(BaseInterrupts): type = 'SparcInterrupts' cxx_class = 'SparcISA::Interrupts' cxx_header = 'arch/sparc/interrupts.hh' diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh index abc899efb..58c701477 100644 --- a/src/arch/sparc/interrupts.hh +++ b/src/arch/sparc/interrupts.hh @@ -32,6 +32,7 @@ #ifndef __ARCH_SPARC_INTERRUPT_HH__ #define __ARCH_SPARC_INTERRUPT_HH__ +#include "arch/generic/interrupts.hh" #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" #include "arch/sparc/registers.hh" @@ -55,7 +56,7 @@ enum InterruptTypes NumInterruptTypes }; -class Interrupts : public SimObject +class Interrupts : public BaseInterrupts { private: BaseCPU * cpu; @@ -79,7 +80,7 @@ class Interrupts : public SimObject return dynamic_cast<const Params *>(_params); } - Interrupts(Params * p) : SimObject(p), cpu(NULL) + Interrupts(Params * p) : BaseInterrupts(p), cpu(NULL) { clearAll(); } diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc index f75d00645..b89f46550 100644 --- a/src/arch/sparc/isa.cc +++ b/src/arch/sparc/isa.cc @@ -32,6 +32,7 @@ #include "arch/sparc/asi.hh" #include "arch/sparc/decoder.hh" +#include "arch/sparc/interrupts.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "cpu/base.hh" |