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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-19 23:54:56 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-19 23:54:56 -0700 |
| commit | 3e8e813218e7779a41bc12caae33db5e239506c9 (patch) | |
| tree | 289f443de0f36590952706257e633132573b1493 /src/arch/x86/SConscript | |
| parent | a3a795769a2590451731f683ba11110f4035ab6b (diff) | |
| download | gem5-3e8e813218e7779a41bc12caae33db5e239506c9.tar.xz | |
CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
--HG--
rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc
rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh
rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
Diffstat (limited to 'src/arch/x86/SConscript')
| -rw-r--r-- | src/arch/x86/SConscript | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 96af0767c..3d1f6f8e3 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -95,6 +95,7 @@ if env['TARGET_ISA'] == 'x86': Source('insts/microregop.cc') Source('insts/static_inst.cc') Source('isa.cc') + Source('nativetrace.cc') Source('pagetable.cc') Source('predecoder.cc') Source('predecoder_tables.cc') @@ -102,6 +103,8 @@ if env['TARGET_ISA'] == 'x86': Source('tlb.cc') Source('utility.cc') + SimObject('X86NativeTrace.py') + SimObject('X86TLB.py') TraceFlag('Predecoder', "Predecoder debug output") TraceFlag('X86', "Generic X86 ISA debugging") |