branch merge

--HG--
extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec

1 files changed, 17 insertions, 0 deletions

diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index ce4db4f4c..dc080f37e 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -53,12 +53,29 @@
 #
 # Authors: Gabe Black
 
+from MemObject import MemObject
 from m5.SimObject import SimObject
 from m5.params import *
+from m5.proxy import *
+from m5 import build_env
+
+if build_env['FULL_SYSTEM']:
+    class X86PagetableWalker(MemObject):
+        type = 'X86PagetableWalker'
+        cxx_namespace = 'X86ISA'
+        cxx_class = 'Walker'
+        port = Port("Port for the hardware table walker")
+        system = Param.System(Parent.any, "system object")
+
 class X86TLB(SimObject):
     type = 'X86TLB'
+    cxx_namespace = 'X86ISA'
+    cxx_class = 'TLB'
     abstract = True
     size = Param.Int("TLB size")
+    if build_env['FULL_SYSTEM']:
+        walker = Param.X86PagetableWalker(\
+                X86PagetableWalker(), "page table walker")
 
 class X86DTB(X86TLB):
     type = 'X86DTB'