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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-10-02 23:00:37 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-10-02 23:00:37 -0700 |
| commit | 504f90f76350ce14debfbfa837423144b0abdbe4 (patch) | |
| tree | 610f9dfdcd624ab6c6a5524dc5dbe3eca073b77d /src/arch/x86/X86TLB.py | |
| parent | f4a932a6b3f5b829dd0e7cb3a596a7e054fd7144 (diff) | |
| download | gem5-504f90f76350ce14debfbfa837423144b0abdbe4.tar.xz | |
X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging.
--HG--
extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af
Diffstat (limited to 'src/arch/x86/X86TLB.py')
| -rw-r--r-- | src/arch/x86/X86TLB.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index f16408e63..ce4db4f4c 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -58,18 +58,18 @@ from m5.params import * class X86TLB(SimObject): type = 'X86TLB' abstract = True - #size = Param.Int("TLB size") + size = Param.Int("TLB size") class X86DTB(X86TLB): type = 'X86DTB' cxx_namespace = 'X86ISA' cxx_class = 'DTB' - #size = 64 + size = 64 class X86ITB(X86TLB): type = 'X86ITB' cxx_namespace = 'X86ISA' cxx_class = 'ITB' - #size = 64 + size = 64 |