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| author | Andreas Sandberg <andreas@sandberg.pp.se> | 2014-03-03 14:44:57 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas@sandberg.pp.se> | 2014-03-03 14:44:57 +0100 |
| commit | be246cef6251113ad25f59cfef37b746c80b11c5 (patch) | |
| tree | 69f072c0f332de811706fa95c49f233d2f65f79d /src/arch/x86/faults.cc | |
| parent | e7d230ede0deb239271a25d227a792ae615daee2 (diff) | |
| download | gem5-be246cef6251113ad25f59cfef37b746c80b11c5.tar.xz | |
x86: Setup correct TSL/TR segment attributes on INIT
The TSL/LDT & TR/TSS segments didn't contain valid attributes. This
caused problems when transfering the state into KVM where invalid
state is a no-go. Fixup the attributes with values from AMD's
architecture programmer's manual.
Diffstat (limited to 'src/arch/x86/faults.cc')
| -rw-r--r-- | src/arch/x86/faults.cc | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc index aa859052e..0cbf2334e 100644 --- a/src/arch/x86/faults.cc +++ b/src/arch/x86/faults.cc @@ -245,15 +245,21 @@ namespace X86ISA tc->setMiscReg(MISCREG_IDTR_BASE, 0); tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); + SegAttr tslAttr = 0; + tslAttr.present = 1; + tslAttr.type = 2; // LDT tc->setMiscReg(MISCREG_TSL, 0); tc->setMiscReg(MISCREG_TSL_BASE, 0); tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff); - tc->setMiscReg(MISCREG_TSL_ATTR, 0); + tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr); + SegAttr trAttr = 0; + trAttr.present = 1; + trAttr.type = 3; // Busy 16-bit TSS tc->setMiscReg(MISCREG_TR, 0); tc->setMiscReg(MISCREG_TR_BASE, 0); tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff); - tc->setMiscReg(MISCREG_TR_ATTR, 0); + tc->setMiscReg(MISCREG_TR_ATTR, trAttr); // This value should be the family/model/stepping of the processor. // (page 418). It should be consistent with the value from CPUID, but |