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author | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:31 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:31 -0800 |
commit | fce45baf178b43c2ea1476967fba3766e9b2ea9d (patch) | |
tree | 1aa3ba357950f9a18e2d7a7e6fd4be8c8d0e5d91 /src/arch/x86/faults.cc | |
parent | f17f3d20be08d25f176138691a29897df54e5cc0 (diff) | |
download | gem5-fce45baf178b43c2ea1476967fba3766e9b2ea9d.tar.xz |
X86: Work on the page table walker, TLB, and related faults.
--HG--
extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
Diffstat (limited to 'src/arch/x86/faults.cc')
-rw-r--r-- | src/arch/x86/faults.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc index 13341f1de..abb5d98d7 100644 --- a/src/arch/x86/faults.cc +++ b/src/arch/x86/faults.cc @@ -93,6 +93,8 @@ #include "arch/x86/isa_traits.hh" #include "mem/page_table.hh" #include "sim/process.hh" +#else +#include "arch/x86/tlb.hh" #endif namespace X86ISA @@ -112,6 +114,19 @@ namespace X86ISA { panic("X86 faults are not implemented!"); } + + void FakeITLBFault::invoke(ThreadContext * tc) + { + // Start the page table walker. + tc->getITBPtr()->walker.start(tc, vaddr); + } + + void FakeDTLBFault::invoke(ThreadContext * tc) + { + // Start the page table walker. + tc->getDTBPtr()->walker.start(tc, vaddr); + } + #else // !FULL_SYSTEM void FakeITLBFault::invoke(ThreadContext * tc) { |