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| author | Swapnil Haria <swapnilster@gmail.com> | 2018-01-15 21:49:17 -0600 |
|---|---|---|
| committer | Jason Lowe-Power <jason@lowepower.com> | 2018-01-23 22:17:46 +0000 |
| commit | 83f2b253989fd6dfc8f48d5368ae351ade91cfc6 (patch) | |
| tree | c11f04427040c2efedb3cbfea8227293861ba8ff /src/arch/x86/isa/decoder/two_byte_opcodes.isa | |
| parent | b074a15ec16b595cbe00cb63e2feff40059b60fb (diff) | |
| download | gem5-83f2b253989fd6dfc8f48d5368ae351ade91cfc6.tar.xz | |
arch-x86: Adding clflush, clflushopt, clwb instructions
This patch adds support for cache flushing instructions in x86.
It piggybacks on support for similar instructions in arm ISA
added by Nikos Nikoleris. I have tested each instruction using
microbenchmarks.
Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d
Reviewed-on: https://gem5-review.googlesource.com/7401
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86/isa/decoder/two_byte_opcodes.isa')
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index f0698ce18..aa60e4c48 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -800,8 +800,16 @@ 0x3: Inst::STMXCSR(Md); 0x4: xsave(); 0x5: xrstor(); - 0x6: Inst::UD2(); - 0x7: clflush(); + 0x6: decode LEGACY_DECODEVAL { + 0x0: Inst::UD2(); + 0x1: Inst::CLWB(Mb); + default: Inst::UD2(); + } + 0x7: decode LEGACY_DECODEVAL { + 0x0: Inst::CLFLUSH(Mb); + 0x1: Inst::CLFLUSHOPT(Mb); + default: Inst::CLFLUSH(Mb); + } } } 0x7: Inst::IMUL(Gv,Ev); |