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authorGabe Black <gblack@eecs.umich.edu>2010-10-22 00:24:15 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-10-22 00:24:15 -0700
commit2eae11be6499effbcf33e4f3ea747a7280adf86c (patch)
tree957658d9253c19dc940f041316dcaccd90b035cc /src/arch/x86/isa/decoder
parent23f6196d61c4f96d5b8f25e3dc8b266d541ecd67 (diff)
downloadgem5-2eae11be6499effbcf33e4f3ea747a7280adf86c.tar.xz
X86: Make nop a regular, non-microcoded instruction.
Code in the CPUs that need a nop to carry a fault can't easily deal with a microcoded nop. This instruction format provides for one that isn't. --HG-- rename : src/arch/x86/isa/formats/syscall.isa => src/arch/x86/isa/formats/nop.isa
Diffstat (limited to 'src/arch/x86/isa/decoder')
-rw-r--r--src/arch/x86/isa/decoder/one_byte_opcodes.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 80f603503..213ddf65a 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -296,7 +296,7 @@
}
}
0x12: decode OPCODE_OP_BOTTOM3 {
- 0x0: NOP(); //XXX repe makes this a "pause"
+ 0x0: NopInst::NOP(); //XXX repe makes this a "pause"
default: XCHG(Bv,rAv);
}
0x13: decode OPCODE_OP_BOTTOM3 {