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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-01-22 00:10:33 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-01-22 00:10:33 -0500 |
| commit | 60c2d98fc088dea76f0cd67588d4efb2ca557136 (patch) | |
| tree | 06020a58cbef4bf902447e286e96fad19b375a4a /src/arch/x86/isa/decoder | |
| parent | f809637011dfde5f14bd8ee07f7c694ab150c253 (diff) | |
| download | gem5-60c2d98fc088dea76f0cd67588d4efb2ca557136.tar.xz | |
X86: Implement and attach the BSR and BSF instructions.
--HG--
extra : convert_revision : be7e11980092e5d1baff0e05d4ec910305966908
Diffstat (limited to 'src/arch/x86/isa/decoder')
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index d4f25775f..d90df6f45 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -766,8 +766,8 @@ } 0x3: BTC(Ev,Gv); } - 0x4: bsf_Gv_Ev(); - 0x5: bsr_Gv_Ev(); + 0x4: Inst::BSF(Gv,Ev); + 0x5: Inst::BSR(Gv,Ev); //The size of the second operand in these instructions should //really be "b" or "w", but it's set to v in order to have a //consistent register size. This shouldn't affect behavior. |