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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:39:10 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:39:10 -0400 |
| commit | 8501a90f59c73896b4eea6d7ce8f1d1cc8685d53 (patch) | |
| tree | 6e8be3ff12c7092a551ca0e816f622083de39f8c /src/arch/x86/isa/decoder | |
| parent | d093fcb07924cc4341b8142c448b905dd94f7125 (diff) | |
| download | gem5-8501a90f59c73896b4eea6d7ce8f1d1cc8685d53.tar.xz | |
X86: Add in some support for the tsc register.
Diffstat (limited to 'src/arch/x86/isa/decoder')
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index 8135a1fdb..e2d968c17 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -317,7 +317,7 @@ } 0x06: decode OPCODE_OP_BOTTOM3 { 0x0: Inst::WRMSR(); - 0x1: rdtsc(); + 0x1: Inst::RDTSC(); 0x2: Inst::RDMSR(); 0x3: rdpmc(); 0x4: sysenter(); |