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| author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-18 15:11:44 +0800 |
| commit | ce003b28a15104574bed634923564a6bd910898d (patch) | |
| tree | d4ac3b5be20f0354e717a4854f981d4a4c21065b /src/arch/x86/isa/insts/system/msrs.py | |
| parent | 4cc9473c971650153d148b74ad67e50e54828a99 (diff) | |
| download | gem5-ce003b28a15104574bed634923564a6bd910898d.tar.xz | |
invisispec-1.0 source
Diffstat (limited to 'src/arch/x86/isa/insts/system/msrs.py')
| -rw-r--r-- | src/arch/x86/isa/insts/system/msrs.py | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py index d0e2675de..f269742dd 100644 --- a/src/arch/x86/isa/insts/system/msrs.py +++ b/src/arch/x86/isa/insts/system/msrs.py @@ -65,4 +65,14 @@ def macroop RDTSC srli t1, t1, 32, dataSize=8 mov rdx, rdx, t1, dataSize=4 }; + + +def macroop RDTSCP +{ + .block + rdtsc t1 + mov rax, rax, t1, dataSize=4 + srli t1, t1, 32, dataSize=8 + mov rdx, rdx, t1, dataSize=4 +}; ''' |