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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:39:10 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:39:10 -0400 |
| commit | 8501a90f59c73896b4eea6d7ce8f1d1cc8685d53 (patch) | |
| tree | 6e8be3ff12c7092a551ca0e816f622083de39f8c /src/arch/x86/isa/insts | |
| parent | d093fcb07924cc4341b8142c448b905dd94f7125 (diff) | |
| download | gem5-8501a90f59c73896b4eea6d7ce8f1d1cc8685d53.tar.xz | |
X86: Add in some support for the tsc register.
Diffstat (limited to 'src/arch/x86/isa/insts')
| -rw-r--r-- | src/arch/x86/isa/insts/system/msrs.py | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py index 1acb4c792..461ed1054 100644 --- a/src/arch/x86/isa/insts/system/msrs.py +++ b/src/arch/x86/isa/insts/system/msrs.py @@ -99,4 +99,12 @@ def macroop WRMSR or t2, t2, t3, dataSize=8 st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4 }; + +def macroop RDTSC +{ + rdtsc t1 + mov rax, rax, t1, dataSize=4 + srli t1, t1, 32, dataSize=8 + mov rdx, rdx, t1, dataSize=4 +}; ''' |