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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 22:55:55 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 22:55:55 -0700 |
| commit | a2e0d539d89643ce5243be9b8a0be4c3bcee7520 (patch) | |
| tree | 977feb73d3ed84cb3f0ad12efdf8e929e4a59397 /src/arch/x86/isa/microasm.isa | |
| parent | 9e8e2f9ec6ae4ea3be8f5280a1ca4cb734e3e068 (diff) | |
| download | gem5-a2e0d539d89643ce5243be9b8a0be4c3bcee7520.tar.xz | |
X86: Add wrval/rdval microops for reading significant miscregs.
Diffstat (limited to 'src/arch/x86/isa/microasm.isa')
| -rw-r--r-- | src/arch/x86/isa/microasm.isa | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 81aa1dafe..f9e0a2fa8 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -159,6 +159,11 @@ let {{ assembler.symbols["CTrue"] = "ConditionTests::True" assembler.symbols["CFalse"] = "ConditionTests::False" + for reg in ('sysenter_cs', 'sysenter_esp', 'sysenter_eip', + 'star', 'lstar', 'cstar', 'sf_mask', + 'kernel_gs_base'): + assembler.symbols[reg] = "MISCREG_%s" % reg.upper() + # Code literal which forces a default 64 bit operand size in 64 bit mode. assembler.symbols["oszIn64Override"] = ''' if (machInst.mode.submode == SixtyFourBitMode && |