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authorKorey Sewell <ksewell@umich.edu>2007-11-15 00:14:20 -0500
committerKorey Sewell <ksewell@umich.edu>2007-11-15 00:14:20 -0500
commit375ddf8d25c3d81a77bd5dd7b70f84a0dbe48fe8 (patch)
tree525cf56502718b69fb7f0e78162a8d5e63256489 /src/arch/x86/isa/microasm.isa
parent2820a448e2bcb861d099b1256087004462b78895 (diff)
parent7c8e4ca3a3b66becbc3e4e7b5e106f5c44b09b6f (diff)
downloadgem5-375ddf8d25c3d81a77bd5dd7b70f84a0dbe48fe8.tar.xz
branch merge
--HG-- extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec
Diffstat (limited to 'src/arch/x86/isa/microasm.isa')
-rw-r--r--src/arch/x86/isa/microasm.isa5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 0c43d4c13..040bb2036 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -108,11 +108,14 @@ let {{
# This segment selects an internal address space mapped to MSRs,
# CPUID info, etc.
- assembler.symbols["intseg"] = "NUM_SEGMENTREGS"
+ assembler.symbols["intseg"] = "SEGMENT_REG_INT"
for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
+ for reg in range(15):
+ assembler.symbols["cr%d" % reg] = "MISCREG_CR%d" % reg
+
for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF'):
assembler.symbols[flag] = flag + "Bit"