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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 03:07:01 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 03:07:01 -0700 |
| commit | b64d0bdeda1662091746c3695b4429fcc6f69342 (patch) | |
| tree | 052e57e8f7b1e6841701e7739c8339722943b3e2 /src/arch/x86/isa/microops/regop.isa | |
| parent | 2914a8eb16cd5a3804bdd500458cff2d2c413869 (diff) | |
| download | gem5-b64d0bdeda1662091746c3695b4429fcc6f69342.tar.xz | |
X86: Fix condition code setting for signed multiplies with negative results.
Diffstat (limited to 'src/arch/x86/isa/microops/regop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index f2e16a515..6921684a4 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -536,6 +536,14 @@ let {{ hiResult -= psrc1; ProdHi = hiResult; ''' + flag_code = ''' + if ((-ProdHi & mask(dataSize * 8)) != + bits(ProdLow, dataSize * 8 - 1)) { + ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); + } else { + ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); + } + ''' class Mul1u(WrRegOp): code = ''' @@ -550,6 +558,13 @@ let {{ ((psrc1_l * psrc2_l) / shifter)) / shifter) + psrc1_h * psrc2_h; ''' + flag_code = ''' + if (ProdHi) { + ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); + } else { + ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); + } + ''' class Mulel(RdRegOp): code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' @@ -561,12 +576,6 @@ let {{ super(RdRegOp, self).__init__(dest, src1, \ "InstRegIndex(NUM_INTREGS)", flags, dataSize) code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' - flag_code = ''' - if (ProdHi) - ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); - else - ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); - ''' # One or two bit divide class Div1(WrRegOp): |