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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-05-22 11:29:53 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-05-22 11:29:53 -0500 |
| commit | 4d4d212ae974b3a3ad6d185902d4896c0233a8d9 (patch) | |
| tree | 4a8203c6677714b5996b6dc22178c61bdb07dec9 /src/arch/x86/isa/microops/specop.isa | |
| parent | 16a559c9c66b3e810860b59c4099527b38a5337e (diff) | |
| download | gem5-4d4d212ae974b3a3ad6d185902d4896c0233a8d9.tar.xz | |
X86: Split Condition Code register
This patch moves the ECF and EZF bits to individual registers (ecfBit and
ezfBit) and the CF and OF bits to cfofFlag registers. This is being done
so as to lower the read after write dependencies on the the condition code
register. Ultimately we will have the following registers [ZAPS], [OF],
[CF], [ECF], [EZF] and [DF]. Note that this is only one part of the
solution for lowering the dependencies. The other part will check whether
or not the condition code register needs to be actually read. This would
be done through a separate patch.
Diffstat (limited to 'src/arch/x86/isa/microops/specop.isa')
| -rw-r--r-- | src/arch/x86/isa/microops/specop.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 5c242e2c9..8092b28b9 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -181,7 +181,8 @@ let {{ iop = InstObjParams("fault", "MicroFaultFlags", "MicroFaultBase", {"code": "", - "cond_test": "checkCondition(ccFlagBits, cc)"}) + "cond_test": "checkCondition(ccFlagBits | cfofBits | \ + ecfBit | ezfBit, cc)"}) exec_output = MicroFaultExecute.subst(iop) header_output = MicroFaultDeclare.subst(iop) decoder_output = MicroFaultConstructor.subst(iop) |