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authorGabe Black <gblack@eecs.umich.edu>2007-09-04 23:32:18 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-09-04 23:32:18 -0700
commit8e3b199cb8fc0109b0bfe87905bb3253b4e7b8c7 (patch)
tree77126ed3bc26c1e36448b5e32b1da49b8f29b306 /src/arch/x86/isa/microops
parentaf4c04c426cca3b73e58ab7464119db28252984c (diff)
downloadgem5-8e3b199cb8fc0109b0bfe87905bb3253b4e7b8c7.tar.xz
X86: Add some SSE floating point/integer conversion microops.
--HG-- extra : convert_revision : 2a1aa16709db940f5f40bbd84ca082f26b03b9c5
Diffstat (limited to 'src/arch/x86/isa/microops')
-rw-r--r--src/arch/x86/isa/microops/regop.isa19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index e169b09d2..3641438f5 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -636,4 +636,23 @@ let {{
class Zext(RegOp):
code = 'DestReg = bits(psrc1, imm8-1, 0);'
+
+ # Conversion microops
+ class ConvOp(RegOp):
+ abstract = True
+ def __init__(self, dest, src1):
+ super(ConvOp, self).__init__(dest, src1, "NUM_INTREGS")
+
+ #FIXME This needs to always use 32 bits unless REX.W is present
+ class cvtf_i2d(ConvOp):
+ code = 'FpDestReg = psrc1;'
+
+ class cvtf_i2d_hi(ConvOp):
+ code = 'FpDestReg = bits(SrcReg1, 63, 32);'
+
+ class cvtf_d2i(ConvOp):
+ code = '''
+ int64_t intSrcReg1 = static_cast<int64_t>(FpSrcReg1);
+ DestReg = merge(DestReg, intSrcReg1, dataSize);
+ '''
}};