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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-03-29 00:49:53 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-03-29 00:49:53 -0700 |
| commit | fd77212b72427f57a800fceface8a85a5b5e4001 (patch) | |
| tree | 51efdd03772f02ca863d357c42f090bf2e38a417 /src/arch/x86/isa/operands.isa | |
| parent | 0d5f6167ffbc78fb5e514a12875d6a873e054871 (diff) | |
| download | gem5-fd77212b72427f57a800fceface8a85a5b5e4001.tar.xz | |
Add code to generate register and immediate based integer op microop classes.
--HG--
extra : convert_revision : 718f941da74dd3b4557cd21e1772879ac21aa9c6
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 20376f38f..36b0ee4df 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -96,7 +96,7 @@ def operand_types {{ }}; def operands {{ - # This is just copied from SPARC, because having no operands confuses - # the parser. - 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1) + 'IntRegOp0': ('IntReg', 'udw', 'regIndex0', 'IsInteger', 1), + 'IntRegOp1': ('IntReg', 'udw', 'regIndex1', 'IsInteger', 2), + 'IntRegOp2': ('IntReg', 'udw', 'regIndex2', 'IsInteger', 2), }}; |