diff options
| author | Gabe Black <gabeblack@google.com> | 2018-11-19 18:14:16 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-31 11:02:05 +0000 |
| commit | 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 (patch) | |
| tree | 22cc08624db8bfa11e4ea7c9817a864ebc2ea706 /src/arch/x86/isa | |
| parent | 25474167e5b247d1b91fbf802c5b396a63ae705e (diff) | |
| download | gem5-5edfb67041ad1c246f4ceca147f06b9db3c0ecc3.tar.xz | |
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.
Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/microops/mediaop.isa | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index f9c6a9f9b..b8ceb02ac 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -245,7 +245,7 @@ let {{ src2, size, destSize, srcSize, ext) op_class = 'SimdMiscOp' code = ''' - int items = sizeof(FloatRegBits) / srcSize; + int items = sizeof(FloatReg) / srcSize; int offset = imm8; if (bits(src1, 0) && (ext & 0x1)) offset -= items; @@ -267,7 +267,7 @@ let {{ src2, size, destSize, srcSize, ext) op_class = 'SimdMiscOp' code = ''' - int items = sizeof(FloatRegBits) / destSize; + int items = sizeof(FloatReg) / destSize; int offset = imm8; if (bits(dest, 0) && (ext & 0x1)) offset -= items; @@ -289,7 +289,7 @@ let {{ "InstRegIndex(0)", size, destSize, srcSize, ext) op_class = 'SimdMiscOp' code = ''' - int items = sizeof(FloatRegBits) / srcSize; + int items = sizeof(FloatReg) / srcSize; uint64_t result = 0; int offset = (ext & 0x1) ? items : 0; for (int i = 0; i < items; i++) { @@ -325,7 +325,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = sizeof(FloatRegBits) / size; + int items = sizeof(FloatReg) / size; int options; int optionBits; if (size == 8) { @@ -342,7 +342,7 @@ let {{ for (int i = 0; i < items; i++) { uint64_t resBits; uint8_t lsel = sel & mask(optionBits); - if (lsel * size >= sizeof(FloatRegBits)) { + if (lsel * size >= sizeof(FloatReg)) { lsel -= options / 2; resBits = bits(FpSrcReg2_uqw, (lsel + 1) * sizeBits - 1, @@ -367,7 +367,7 @@ let {{ code = ''' assert(srcSize == destSize); int size = destSize; - int items = (sizeof(FloatRegBits) / size) / 2; + int items = (sizeof(FloatReg) / size) / 2; int offset = ext ? items : 0; uint64_t result = 0; for (int i = 0; i < items; i++) { @@ -393,7 +393,7 @@ let {{ op_class = 'SimdMiscOp' code = ''' assert(srcSize == destSize * 2); - int items = (sizeof(FloatRegBits) / destSize); + int items = (sizeof(FloatReg) / destSize); int destBits = destSize * 8; int srcBits = srcSize * 8; uint64_t result = 0; @@ -1091,7 +1091,7 @@ let {{ op_class = 'SimdAddOp' code = ''' int srcBits = srcSize * 8; - int items = sizeof(FloatRegBits) / srcSize; + int items = sizeof(FloatReg) / srcSize; uint64_t sum = 0; for (int i = 0; i < items; i++) { |