mem: adding architectural page table support for SE mode

This patch enables the use of page tables that are stored in system memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.

1 files changed, 9 insertions, 0 deletions

diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh
index 6a221e792..2fb051953 100644
--- a/src/arch/x86/process.hh
+++ b/src/arch/x86/process.hh
@@ -44,6 +44,7 @@
 #include <vector>
 
 #include "sim/process.hh"
+#include "mem/multi_level_page_table.hh"
 
 class SyscallDesc;
 
@@ -133,6 +134,14 @@ namespace X86ISA
         X86ISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
         void setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val);
     };
+
+    /**
+     * Declaration of architectural page table for x86.
+     *
+     * These page tables are stored in system memory and respect x86 specification.
+     */
+    typedef MultiLevelPageTable<PageTableOps> ArchPageTable;
+
 }
 
 #endif // __ARCH_X86_PROCESS_HH__