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| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-02-11 10:23:27 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-02-11 10:23:27 -0500 |
| commit | 550c31849024a2184887df87aae39617ebfe0d6a (patch) | |
| tree | 53cc5e91d0961b0215c614141fdc380b30c76951 /src/arch/x86/tlb.hh | |
| parent | 9e6f803254cbf3f5f491775debdc6593c3329da8 (diff) | |
| download | gem5-550c31849024a2184887df87aae39617ebfe0d6a.tar.xz | |
sim: Move the BaseTLB to src/arch/generic/
The TLB-related code is generally architecture dependent and should
live in the arch directory to signify that.
--HG--
rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py
rename : src/sim/tlb.cc => src/arch/generic/tlb.cc
rename : src/sim/tlb.hh => src/arch/generic/tlb.hh
Diffstat (limited to 'src/arch/x86/tlb.hh')
| -rw-r--r-- | src/arch/x86/tlb.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index e1089f90c..77f9fc49d 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -44,6 +44,7 @@ #include <string> #include <vector> +#include "arch/generic/tlb.hh" #include "arch/x86/regs/segment.hh" #include "arch/x86/pagetable.hh" #include "base/trie.hh" @@ -51,7 +52,6 @@ #include "mem/request.hh" #include "params/X86TLB.hh" #include "sim/sim_object.hh" -#include "sim/tlb.hh" class ThreadContext; class Packet; |