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| author | Swapnil Haria <swapnilster@gmail.com> | 2017-06-13 09:46:58 -0500 |
|---|---|---|
| committer | Sean Wilson <spwilson2@wisc.edu> | 2017-07-17 15:16:16 +0000 |
| commit | c305e150048b2ac92891b1054f0c65a6c3374e90 (patch) | |
| tree | 624e3cd3af17c63c4e8fddce2e54c202879a19cd /src/arch/x86/tlb.hh | |
| parent | d2ab7234685bd8c007d10a525f67265a1fcb5fa4 (diff) | |
| download | gem5-c305e150048b2ac92891b1054f0c65a6c3374e90.tar.xz | |
x86: Add stats to X86 TLB
Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3980
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/x86/tlb.hh')
| -rw-r--r-- | src/arch/x86/tlb.hh | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index a134ad427..09cd6edc7 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -100,6 +100,12 @@ namespace X86ISA TlbEntryTrie trie; uint64_t lruSeq; + // Statistics + Stats::Scalar rdAccesses; + Stats::Scalar wrAccesses; + Stats::Scalar rdMisses; + Stats::Scalar wrMisses; + Fault translateInt(RequestPtr req, ThreadContext *tc); Fault translate(RequestPtr req, ThreadContext *tc, @@ -142,6 +148,11 @@ namespace X86ISA TlbEntry * insert(Addr vpn, TlbEntry &entry); + /* + * Function to register Stats + */ + void regStats(); + // Checkpointing void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; |