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authorGabe Black <gblack@eecs.umich.edu>2009-08-17 18:15:21 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-08-17 18:15:21 -0700
commit33cb4c2f09d7ad21cf37bab6ce1f846a049e121e (patch)
tree1d80c03cba18c1aa2cf998509fa9b0838d8e4c3d /src/arch/x86
parent3a4438a8683e73fc5fb6195a627372a5de2c5a99 (diff)
downloadgem5-33cb4c2f09d7ad21cf37bab6ce1f846a049e121e.tar.xz
X86: Use suffixes to differentiate XMM/MMX/GPR operands.
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py6
-rw-r--r--src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py6
-rw-r--r--src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py6
-rw-r--r--src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py6
-rw-r--r--src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py6
-rw-r--r--src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_rflags.py6
-rw-r--r--src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py2
-rw-r--r--src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py30
-rw-r--r--src/arch/x86/isa/insts/simd128/floating_point/logical/exclusive_or.py6
-rw-r--r--src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py6
-rw-r--r--src/arch/x86/isa/specialize.isa25
11 files changed, 61 insertions, 44 deletions
diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py
index c1764ff12..abe09cf34 100644
--- a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py
@@ -58,16 +58,16 @@ microcode = '''
# ADDPD
# ADDSS
-def macroop ADDSD_R_R {
+def macroop ADDSD_XMM_XMM {
addfp xmml, xmml, xmmlm
};
-def macroop ADDSD_R_M {
+def macroop ADDSD_XMM_M {
ldfp ufp1, seg, sib, disp
addfp xmml, xmml, ufp1
};
-def macroop ADDSD_R_P {
+def macroop ADDSD_XMM_P {
rdip t7
ldfp ufp1, seg, riprel, disp
addfp xmml, xmml, ufp1
diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py
index 31f336696..dad2e6510 100644
--- a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py
@@ -58,16 +58,16 @@ microcode = '''
# DIVPD
# DIVSS
-def macroop DIVSD_R_R {
+def macroop DIVSD_XMM_XMM {
divfp xmml, xmml, xmmlm
};
-def macroop DIVSD_R_M {
+def macroop DIVSD_XMM_M {
ldfp ufp1, seg, sib, disp
divfp xmml, xmml, ufp1
};
-def macroop DIVSD_R_P {
+def macroop DIVSD_XMM_P {
rdip t7
ldfp ufp1, seg, riprel, disp
divfp xmml, xmml, ufp1
diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py
index 1a53eb27f..5310cdd01 100644
--- a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py
@@ -58,16 +58,16 @@ microcode = '''
# MULPD
# MULSS
-def macroop MULSD_R_R {
+def macroop MULSD_XMM_XMM {
mulfp xmml, xmml, xmmlm
};
-def macroop MULSD_R_M {
+def macroop MULSD_XMM_M {
ldfp ufp1, seg, sib, disp
mulfp xmml, xmml, ufp1
};
-def macroop MULSD_R_P {
+def macroop MULSD_XMM_P {
rdip t7
ldfp ufp1, seg, riprel, disp
mulfp xmml, xmml, ufp1
diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py
index 4f67aee88..537aa8ae9 100644
--- a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py
@@ -58,16 +58,16 @@ microcode = '''
# SQRTPD
# SQRTSS
-def macroop SQRTSD_R_R {
+def macroop SQRTSD_XMM_XMM {
sqrtfp xmml, xmml, xmmlm
};
-def macroop SQRTSD_R_M {
+def macroop SQRTSD_XMM_M {
ldfp ufp1, seg, sib, disp
sqrtfp xmml, xmml, ufp1
};
-def macroop SQRTSD_R_P {
+def macroop SQRTSD_XMM_P {
rdip t7
ldfp ufp1, seg, riprel, disp
sqrtfp xmml, xmml, ufp1
diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py
index 4f73fa899..afb477023 100644
--- a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py
@@ -58,16 +58,16 @@ microcode = '''
# SUBPD
# SUBSS
-def macroop SUBSD_R_R {
+def macroop SUBSD_XMM_XMM {
subfp xmml, xmml, xmmlm
};
-def macroop SUBSD_R_M {
+def macroop SUBSD_XMM_M {
ldfp ufp1, seg, sib, disp
subfp xmml, xmml, ufp1
};
-def macroop SUBSD_R_P {
+def macroop SUBSD_XMM_P {
rdip t7
ldfp ufp1, seg, riprel, disp
subfp xmml, xmml, ufp1
diff --git a/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_rflags.py b/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_rflags.py
index e05018495..0f6ef2ba2 100644
--- a/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_rflags.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_rflags.py
@@ -58,16 +58,16 @@ microcode = '''
# COMISD
# UCOMISS
-def macroop UCOMISD_R_R {
+def macroop UCOMISD_XMM_XMM {
compfp xmml, xmmlm
};
-def macroop UCOMISD_R_M {
+def macroop UCOMISD_XMM_M {
ldfp ufp1, seg, sib, disp
compfp xmml, ufp1
};
-def macroop UCOMISD_R_P {
+def macroop UCOMISD_XMM_P {
rdip t7
ldfp ufp1, seg, riprel, disp
compfp xmml, ufp1
diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py
index 8d5f4e659..80eae8331 100644
--- a/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py
@@ -58,7 +58,7 @@ microcode = '''
# CVTSD2SI
# CVTTSS2SI
-def macroop CVTTSD2SI_R_R {
+def macroop CVTTSD2SI_R_XMM {
cvtf_d2i reg, xmmlm
};
diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
index 76279fc70..1924f8f8c 100644
--- a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
@@ -54,33 +54,33 @@
# Authors: Gabe Black
microcode = '''
-def macroop MOVAPS_R_M {
+def macroop MOVAPS_XMM_M {
# Check low address.
ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
ldfp xmml, seg, sib, disp, dataSize=8
};
-def macroop MOVAPS_R_P {
+def macroop MOVAPS_XMM_P {
rdip t7
# Check low address.
ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
ldfp xmml, seg, riprel, disp, dataSize=8
};
-def macroop MOVAPS_M_R {
+def macroop MOVAPS_M_XMM {
# Check low address.
stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
stfp xmml, seg, sib, disp, dataSize=8
};
-def macroop MOVAPS_P_R {
+def macroop MOVAPS_P_XMM {
rdip t7
# Check low address.
stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
stfp xmml, seg, riprel, disp, dataSize=8
};
-def macroop MOVAPS_R_R {
+def macroop MOVAPS_XMM_XMM {
# Check low address.
movfp xmml, xmmlm, dataSize=8
movfp xmmh, xmmhm, dataSize=8
@@ -93,25 +93,25 @@ def macroop MOVAPS_R_R {
# MOVHPD
# MOVLPS
-def macroop MOVLPD_R_M {
+def macroop MOVLPD_XMM_M {
ldfp xmml, seg, sib, disp, dataSize=8
};
-def macroop MOVLPD_R_P {
+def macroop MOVLPD_XMM_P {
rdip t7
ldfp xmml, seg, riprel, disp, dataSize=8
};
-def macroop MOVLPD_M_R {
+def macroop MOVLPD_M_XMM {
stfp xmml, seg, sib, disp, dataSize=8
};
-def macroop MOVLPD_P_R {
+def macroop MOVLPD_P_XMM {
rdip t7
stfp xmml, seg, riprel, disp, dataSize=8
};
-def macroop MOVLPD_R_R {
+def macroop MOVLPD_XMM_XMM {
movfp xmml, xmmlm, dataSize=8
};
@@ -119,27 +119,27 @@ def macroop MOVLPD_R_R {
# MOVLHPS
# MOVSS
-def macroop MOVSD_R_M {
+def macroop MOVSD_XMM_M {
# Zero xmmh
ldfp xmml, seg, sib, disp, dataSize=8
};
-def macroop MOVSD_R_P {
+def macroop MOVSD_XMM_P {
rdip t7
# Zero xmmh
ldfp xmml, seg, riprel, disp, dataSize=8
};
-def macroop MOVSD_M_R {
+def macroop MOVSD_M_XMM {
stfp xmml, seg, sib, disp, dataSize=8
};
-def macroop MOVSD_P_R {
+def macroop MOVSD_P_XMM {
rdip t7
stfp xmml, seg, riprel, disp, dataSize=8
};
-def macroop MOVSD_R_R {
+def macroop MOVSD_XMM_XMM {
movfp xmml, xmmlm, dataSize=8
};
'''
diff --git a/src/arch/x86/isa/insts/simd128/floating_point/logical/exclusive_or.py b/src/arch/x86/isa/insts/simd128/floating_point/logical/exclusive_or.py
index 974771e98..5eed80393 100644
--- a/src/arch/x86/isa/insts/simd128/floating_point/logical/exclusive_or.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/logical/exclusive_or.py
@@ -56,19 +56,19 @@
microcode = '''
# XORPS
-def macroop XORPD_R_R {
+def macroop XORPD_XMM_XMM {
xorfp xmml, xmml, xmmlm
xorfp xmmh, xmmh, xmmhm
};
-def macroop XORPD_R_M {
+def macroop XORPD_XMM_M {
ldfp ufp1, seg, sib, disp
ldfp ufp2, seg, sib, "DISPLACEMENT + 8"
xorfp xmml, xmml, ufp1
xorfp xmmh, xmmh, ufp2
};
-def macroop XORPD_R_P {
+def macroop XORPD_XMM_P {
rdip t7
ldfp ufp1, seg, riprel, disp
ldfp ufp2, seg, riprel, "DISPLACEMENT + 8"
diff --git a/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py b/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py
index b667055dc..a900b374a 100644
--- a/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py
+++ b/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py
@@ -56,16 +56,16 @@
microcode = '''
# CVTSI2SS
-def macroop CVTSI2SD_R_R {
+def macroop CVTSI2SD_XMM_R {
cvtf_i2d xmml, regm
};
-def macroop CVTSI2SD_R_M {
+def macroop CVTSI2SD_XMM_M {
ld t1, seg, sib, disp
cvtf_i2d xmml, t1
};
-def macroop CVTSI2SD_R_P {
+def macroop CVTSI2SD_XMM_P {
rdip t7
ld t1, seg, riprel, disp
cvtf_i2d xmml, t1
diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa
index b74363470..4ebba6981 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -190,7 +190,12 @@ let {{
env.addReg(ModRMRegIndex)
env.addToDisassembly(
"printReg(out, %s, regSize);\n" % ModRMRegIndex)
- Name += "_R"
+ if opType.tag == "P":
+ Name += "_MMX"
+ elif opType.tag == "V":
+ Name += "_XMM"
+ else:
+ Name += "_R"
elif opType.tag in ("E", "Q", "W"):
# This might refer to memory or to a register. We need to
# divide it up farther.
@@ -202,9 +207,16 @@ let {{
# modrm addressing.
memEnv = copy.copy(env)
memEnv.doModRM = True
+ regSuffix = "_R"
+ if opType.tag == "Q":
+ regSuffix = "_MMX"
+ elif opType.tag == "W":
+ regSuffix = "_XMM"
return doSplitDecode("MODRM_MOD",
- {"3" : (specializeInst, Name + "_R", copy.copy(opTypes), regEnv)},
- (doRipRelativeDecode, Name, copy.copy(opTypes), memEnv))
+ {"3" : (specializeInst, Name + regSuffix,
+ copy.copy(opTypes), regEnv)},
+ (doRipRelativeDecode, Name,
+ copy.copy(opTypes), memEnv))
elif opType.tag in ("I", "J"):
# Immediates
env.addToDisassembly(
@@ -218,7 +230,12 @@ let {{
env.addReg(ModRMRMIndex)
env.addToDisassembly(
"printReg(out, %s, regSize);\n" % ModRMRMIndex)
- Name += "_R"
+ if opType.tag == "PR":
+ Name += "_MMX"
+ elif opType.tag == "VR":
+ Name += "_XMM"
+ else:
+ Name += "_R"
elif opType.tag in ("X", "Y"):
# This type of memory addressing is for string instructions.
# They'll use the right index and segment internally.