ISA: Make the decode function part of the ISA's decoder.

5 files changed, 61 insertions, 6 deletions

diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 3bd968e21..27b12fe20 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -44,6 +44,7 @@ Import('*')
 
 if env['TARGET_ISA'] == 'x86':
     Source('cpuid.cc')
+    Source('decoder.cc')
     Source('emulenv.cc')
     Source('faults.cc')
     Source('insts/badmicroop.cc')
diff --git a/src/arch/x86/decoder.cc b/src/arch/x86/decoder.cc
new file mode 100644
index 000000000..469858301
--- /dev/null
+++ b/src/arch/x86/decoder.cc
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/decoder.hh"
+
+namespace X86ISA
+{
+
+DecodeCache Decoder::defaultCache;
+
+}
diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index 6c8c122f8..769284adb 100644
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -31,13 +31,31 @@
 #ifndef __ARCH_X86_DECODER_HH__
 #define __ARCH_X86_DECODER_HH__
 
-#include "arch/generic/decoder.hh"
+#include "arch/types.hh"
+#include "cpu/decode_cache.hh"
+#include "cpu/static_inst_fwd.hh"
 
 namespace X86ISA
 {
 
-class Decoder : public GenericISA::Decoder
-{};
+class Decoder
+{
+  protected:
+    /// A cache of decoded instruction objects.
+    static DecodeCache defaultCache;
+
+  public:
+    StaticInstPtr decodeInst(ExtMachInst mach_inst);
+
+    /// Decode a machine instruction.
+    /// @param mach_inst The binary instruction to decode.
+    /// @retval A pointer to the corresponding StaticInst object.
+    StaticInstPtr
+    decode(ExtMachInst mach_inst, Addr addr)
+    {
+        return defaultCache.decode(this, mach_inst, addr);
+    }
+};
 
 } // namespace X86ISA
 
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 127b8b5fb..eda2ebceb 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -73,6 +73,7 @@ using X86ISA::InstRegIndex;
 }};
 
 output decoder {{
+#include "arch/x86/decoder.hh"
 #include "arch/x86/regs/float.hh"
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/regs/segment.hh"
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 34c5b5ebc..383e56eee 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -43,7 +43,6 @@
 #include "arch/x86/types.hh"
 #include "arch/x86/x86_traits.hh"
 #include "base/types.hh"
-#include "cpu/static_inst_fwd.hh"
 
 namespace LittleEndianGuest {}
 
@@ -69,8 +68,6 @@ namespace X86ISA
 
     const int BranchPredAddrShiftAmt = 0;
 
-    StaticInstPtr decodeInst(ExtMachInst);
-
     // Memory accesses can be unaligned
     const bool HasUnalignedMemAcc = true;