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authorGabe Black <gblack@eecs.umich.edu>2007-11-12 14:38:45 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-11-12 14:38:45 -0800
commitf9ddb894dd92d6cc5601d65a3c58dc5dd73f7ac7 (patch)
treedecee5793bb85d01031164d6df674d04d9c36c36 /src/arch/x86
parent6d4ba8de34e4427a0488e6bc0a9f5b9ec5b1a265 (diff)
downloadgem5-f9ddb894dd92d6cc5601d65a3c58dc5dd73f7ac7.tar.xz
X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.
--HG-- extra : convert_revision : 08bd7b4ff183038c016612d04ac73b20a255d141
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py2
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py2
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_transfer/move.py30
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py4
-rw-r--r--src/arch/x86/isa/insts/general_purpose/input_output/general_io.py4
-rw-r--r--src/arch/x86/isa/insts/general_purpose/input_output/string_io.py8
-rw-r--r--src/arch/x86/isa/microops/regop.isa18
7 files changed, 39 insertions, 29 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py
index 9a7c226af..ae3c6cc6f 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py
@@ -55,7 +55,7 @@
microcode = '''
def macroop CDQE_R {
- sext reg, reg, "env.dataSize << 2"
+ sexti reg, reg, "env.dataSize << 2 - 1"
};
def macroop CQO_R_R {
diff --git a/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py
index c2ccb9d19..d6ae7885a 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py
@@ -55,7 +55,7 @@
microcode = '''
def macroop XLAT {
- zext t1, rax, 8
+ zexti t1, rax, 7
# Here, t1 can be used directly. The value of al is supposed to be treated
# as unsigned. Since we zero extended it from 8 bits above and the address
# size has to be at least 16 bits, t1 will not be sign extended.
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
index 04f9ea12a..ada7f28a3 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
@@ -111,48 +111,48 @@ def macroop MOV_P_I {
#
def macroop MOVSXD_R_R {
- sext reg, regm, 32
+ sexti reg, regm, 31
};
def macroop MOVSXD_R_M {
ld t1, seg, sib, disp, dataSize=4
- sext reg, t1, 32
+ sexti reg, t1, 31
};
def macroop MOVSXD_R_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=4
- sext reg, t1, 32
+ sexti reg, t1, 31
};
def macroop MOVSX_B_R_R {
- sext reg, regm, 8
+ sexti reg, regm, 7
};
def macroop MOVSX_B_R_M {
ld reg, seg, sib, disp, dataSize=1
- sext reg, reg, 8
+ sexti reg, reg, 7
};
def macroop MOVSX_B_R_P {
rdip t7
ld reg, seg, riprel, disp, dataSize=1
- sext reg, reg, 8
+ sexti reg, reg, 7
};
def macroop MOVSX_W_R_R {
- sext reg, regm, 16
+ sexti reg, regm, 15
};
def macroop MOVSX_W_R_M {
ld reg, seg, sib, disp, dataSize=2
- sext reg, reg, 16
+ sexti reg, reg, 15
};
def macroop MOVSX_W_R_P {
rdip t7
ld reg, seg, riprel, disp, dataSize=2
- sext reg, reg, 16
+ sexti reg, reg, 15
};
#
@@ -160,33 +160,33 @@ def macroop MOVSX_W_R_P {
#
def macroop MOVZX_B_R_R {
- zext reg, regm, 8
+ zexti reg, regm, 7
};
def macroop MOVZX_B_R_M {
ld t1, seg, sib, disp, dataSize=1
- zext reg, t1, 8
+ zexti reg, t1, 7
};
def macroop MOVZX_B_R_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=1
- zext reg, t1, 8
+ zexti reg, t1, 7
};
def macroop MOVZX_W_R_R {
- zext reg, regm, 16
+ zexti reg, regm, 15
};
def macroop MOVZX_W_R_M {
ld t1, seg, sib, disp, dataSize=2
- zext reg, t1, 16
+ zexti reg, t1, 15
};
def macroop MOVZX_W_R_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=2
- zext reg, t1, 16
+ zexti reg, t1, 15
};
'''
#let {{
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
index 5884d68c2..6c51f3171 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
@@ -162,9 +162,9 @@ def macroop ENTER_I_I {
# Pull the different components out of the immediate
limm t1, imm
- zext t2, t1, 16, dataSize=2
+ zexti t2, t1, 15, dataSize=2
srl t1, t1, 16
- zext t1, t1, 6
+ zexti t1, t1, 5
# t1 is now the masked nesting level, and t2 is the amount of storage.
# Push rbp.
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
index c01a11035..75a361eb7 100644
--- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
@@ -62,7 +62,7 @@ microcode = '''
def macroop IN_R_R {
limm t1, "IntAddrPrefixIO"
- zext t2, regm, 16, dataSize=2
+ zexti t2, regm, 15, dataSize=2
ld reg, intseg, [1, t1, t2], addressSize=8
};
@@ -74,7 +74,7 @@ microcode = '''
def macroop OUT_R_R {
limm t1, "IntAddrPrefixIO"
- zext t2, reg, 16, dataSize=2
+ zexti t2, reg, 15, dataSize=2
st regm, intseg, [1, t1, t2], addressSize=8
};
'''
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
index a8acbbc39..b44203d9c 100644
--- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
@@ -62,7 +62,7 @@ def macroop INS_M_R {
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
limm t1, "IntAddrPrefixIO"
- zext t2, reg, 16, dataSize=2
+ zexti t2, reg, 15, dataSize=2
ld t6, intseg, [1, t1, t2], addressSize=8
st t6, es, [1, t0, rdi]
@@ -78,7 +78,7 @@ def macroop INS_E_M_R {
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
limm t1, "IntAddrPrefixIO"
- zext t2, reg, 16, dataSize=2
+ zexti t2, reg, 15, dataSize=2
topOfLoop:
ld t6, intseg, [1, t1, t2], addressSize=8
@@ -98,7 +98,7 @@ def macroop OUTS_R_M {
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
limm t1, "IntAddrPrefixIO"
- zext t2, reg, 16, dataSize=2
+ zexti t2, reg, 15, dataSize=2
ld t6, ds, [1, t0, rsi]
st t6, intseg, [1, t1, t2], addressSize=8
@@ -114,7 +114,7 @@ def macroop OUTS_E_R_M {
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
limm t1, "IntAddrPrefixIO"
- zext t2, reg, 16, dataSize=2
+ zexti t2, reg, 15, dataSize=2
topOfLoop:
ld t6, ds, [1, t0, rsi]
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 892c44487..b5e17d36d 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -318,7 +318,7 @@ let {{
# If there's something optional to do with flags, generate
# a version without it and fix up this version to use it.
- if flag_code is not "" or cond_check is not "true":
+ if flag_code != "" or cond_check != "true":
self.buildCppClasses(name, Name, suffix,
code, "", "true", else_code)
suffix = "Flags" + suffix
@@ -866,12 +866,22 @@ let {{
class Sext(RegOp):
code = '''
IntReg val = psrc1;
- int sign_bit = bits(val, imm8-1, imm8-1);
- uint64_t maskVal = mask(imm8);
+ // Mask the bit position so that it wraps.
+ int bitPos = op2 & (dataSize * 8 - 1);
+ int sign_bit = bits(val, bitPos, bitPos);
+ uint64_t maskVal = mask(bitPos+1);
val = sign_bit ? (val | ~maskVal) : (val & maskVal);
DestReg = merge(DestReg, val, dataSize);
'''
+ flag_code = '''
+ if (!sign_bit)
+ ccFlagBits = ccFlagBits &
+ ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
+ else
+ ccFlagBits = ccFlagBits |
+ (ext & (CFBit | ECFBit | ZFBit | EZFBit));
+ '''
class Zext(RegOp):
- code = 'DestReg = bits(psrc1, imm8-1, 0);'
+ code = 'DestReg = bits(psrc1, op2, 0);'
}};