Merge with head, hopefully the last time for this batch.

22 files changed, 166 insertions, 42 deletions

diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 623eafb8a..f1199b9b6 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -64,7 +64,7 @@ TLB::TLB(const Params *p)
     : BaseTLB(p), size(p->size), nlu(0)
 {
     table = new TlbEntry[size];
-    memset(table, 0, sizeof(TlbEntry[size]));
+    memset(table, 0, sizeof(TlbEntry) * size);
     flushCache();
 }
 
@@ -280,7 +280,7 @@ void
 TLB::flushAll()
 {
     DPRINTF(TLB, "flushAll\n");
-    memset(table, 0, sizeof(TlbEntry[size]));
+    memset(table, 0, sizeof(TlbEntry) * size);
     flushCache();
     lookupTable.clear();
     nlu = 0;
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index b6261769f..1d4b6c6f8 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -49,7 +49,7 @@ class ThreadContext;
 
 namespace AlphaISA {
 
-class TlbEntry;
+struct TlbEntry;
 
 class TLB : public BaseTLB
 {
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index d65555822..c36024ecd 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -46,6 +46,7 @@
 #include "arch/arm/utility.hh"
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
+#include "sim/byteswap.hh"
 #include "sim/full_system.hh"
 
 namespace ArmISA
diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh
index 57b74d040..b3582a351 100644
--- a/src/arch/arm/insts/vfp.hh
+++ b/src/arch/arm/insts/vfp.hh
@@ -107,6 +107,9 @@ enum VfpRoundingMode
     VfpRoundZero = 3
 };
 
+static inline float bitsToFp(uint64_t, float);
+static inline uint32_t fpToBits(float);
+
 template <class fpType>
 static inline bool
 flushToZero(fpType &op)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b504550a1..5c2478946 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2011 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -39,12 +39,17 @@
  */
 
 #include "arch/arm/isa.hh"
+#include "config/use_checker.hh"
 #include "debug/Arm.hh"
 #include "debug/MiscRegs.hh"
 #include "sim/faults.hh"
 #include "sim/stat_control.hh"
 #include "sim/system.hh"
 
+#if USE_CHECKER
+#include "cpu/checker/cpu.hh"
+#endif
+
 namespace ArmISA
 {
 
@@ -279,7 +284,11 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
         PCState pc = tc->pcState();
         pc.nextThumb(cpsr.t);
         pc.nextJazelle(cpsr.j);
+#if USE_CHECKER
+        tc->pcStateNoRecord(pc);
+#else
         tc->pcState(pc);
+#endif //USE_CHECKER
     } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
         misc_reg < MISCREG_CP15_END) {
         panic("Unimplemented CP15 register %s wrote with %#x.\n",
@@ -382,6 +391,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                     oc = sys->getThreadContext(x);
                     oc->getDTBPtr()->allCpusCaching();
                     oc->getITBPtr()->allCpusCaching();
+#if USE_CHECKER
+                    CheckerCPU *checker =
+                        dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+                    if (checker) {
+                        checker->getDTBPtr()->allCpusCaching();
+                        checker->getITBPtr()->allCpusCaching();
+                    }
+#endif
                 }
                 return;
             }
@@ -399,6 +416,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 assert(oc->getITBPtr() && oc->getDTBPtr());
                 oc->getITBPtr()->flushAll();
                 oc->getDTBPtr()->flushAll();
+#if USE_CHECKER
+                CheckerCPU *checker =
+                    dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+                if (checker) {
+                    checker->getITBPtr()->flushAll();
+                    checker->getDTBPtr()->flushAll();
+                }
+#endif
             }
             return;
           case MISCREG_ITLBIALL:
@@ -417,6 +442,16 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                         bits(newVal, 7,0));
                 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
                         bits(newVal, 7,0));
+#if USE_CHECKER
+                CheckerCPU *checker =
+                    dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+                if (checker) {
+                    checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
+                            bits(newVal, 7,0));
+                    checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
+                            bits(newVal, 7,0));
+                }
+#endif
             }
             return;
           case MISCREG_TLBIASIDIS:
@@ -427,6 +462,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 assert(oc->getITBPtr() && oc->getDTBPtr());
                 oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
                 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
+#if USE_CHECKER
+                CheckerCPU *checker =
+                    dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+                if (checker) {
+                    checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
+                    checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
+                }
+#endif
             }
             return;
           case MISCREG_TLBIMVAAIS:
@@ -437,6 +480,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 assert(oc->getITBPtr() && oc->getDTBPtr());
                 oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
                 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
+#if USE_CHECKER
+                CheckerCPU *checker =
+                    dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+                if (checker) {
+                    checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
+                    checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
+                }
+#endif
             }
             return;
           case MISCREG_ITLBIMVA:
diff --git a/src/arch/arm/isa/formats/m5ops.isa b/src/arch/arm/isa/formats/m5ops.isa
index 3b08acad7..1eb7d3f65 100644
--- a/src/arch/arm/isa/formats/m5ops.isa
+++ b/src/arch/arm/isa/formats/m5ops.isa
@@ -59,6 +59,7 @@ def format M5ops() {{
             case 0x41: return new Dumpstats(machInst);
             case 0x42: return new Dumpresetstats(machInst);
             case 0x43: return new M5checkpoint(machInst);
+            case 0x4F: return new M5writefile(machInst);
             case 0x50: return new M5readfile(machInst);
             case 0x51: return new M5break(machInst);
             case 0x52: return new M5switchcpu(machInst);
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index da2e10886..a32bf6dfc 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -243,7 +243,7 @@ let {{
     m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
                            { "code": m5checkpoint_code,
                              "predicate_test": predicateTest },
-                             ["IsNonSpeculative"])
+                             ["IsNonSpeculative", "IsUnverifiable"])
     header_output += BasicDeclare.subst(m5checkpointIop)
     decoder_output += BasicConstructor.subst(m5checkpointIop)
     exec_output += PredOpExecute.subst(m5checkpointIop)
@@ -256,11 +256,27 @@ let {{
     m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
                            { "code": m5readfileCode,
                              "predicate_test": predicateTest },
-                             ["IsNonSpeculative"])
+                             ["IsNonSpeculative", "IsUnverifiable"])
     header_output += BasicDeclare.subst(m5readfileIop)
     decoder_output += BasicConstructor.subst(m5readfileIop)
     exec_output += PredOpExecute.subst(m5readfileIop)
 
+    m5writefileCode = '''
+    int n = 4;
+    uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
+    n = 6;
+    Addr filenameAddr = getArgument(xc->tcBase(), n, sizeof(Addr), false);
+    R0 = PseudoInst::writefile(xc->tcBase(), R0, join32to64(R3,R2), offset,
+                                filenameAddr);
+    '''
+    m5writefileIop = InstObjParams("m5writefile", "M5writefile", "PredOp",
+                           { "code": m5writefileCode,
+                             "predicate_test": predicateTest },
+                             ["IsNonSpeculative"])
+    header_output += BasicDeclare.subst(m5writefileIop)
+    decoder_output += BasicConstructor.subst(m5writefileIop)
+    exec_output += PredOpExecute.subst(m5writefileIop)
+
     m5breakIop = InstObjParams("m5break", "M5break", "PredOp",
                            { "code": "PseudoInst::debugbreak(xc->tcBase());",
                              "predicate_test": predicateTest },
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index b671843cf..d8ee5e88d 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -521,7 +521,8 @@ let {{
             { "code" : wfeCode,
               "pred_fixup" : wfePredFixUpCode,
               "predicate_test" : predicateTest },
-            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
+            ["IsNonSpeculative", "IsQuiesce",
+             "IsSerializeAfter", "IsUnverifiable"])
     header_output += BasicDeclare.subst(wfeIop)
     decoder_output += BasicConstructor.subst(wfeIop)
     exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
@@ -536,7 +537,8 @@ let {{
     '''
     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
             { "code" : wfiCode, "predicate_test" : predicateTest },
-            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
+            ["IsNonSpeculative", "IsQuiesce",
+             "IsSerializeAfter", "IsUnverifiable"])
     header_output += BasicDeclare.subst(wfiIop)
     decoder_output += BasicConstructor.subst(wfiIop)
     exec_output += QuiescePredOpExecute.subst(wfiIop)
@@ -557,7 +559,7 @@ let {{
     '''
     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
             { "code" : sevCode, "predicate_test" : predicateTest },
-            ["IsNonSpeculative", "IsSquashAfter"])
+            ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
     header_output += BasicDeclare.subst(sevIop)
     decoder_output += BasicConstructor.subst(sevIop)
     exec_output += PredOpExecute.subst(sevIop)
diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa
index 0728b66e3..b3878b89a 100644
--- a/src/arch/arm/isa/templates/basic.isa
+++ b/src/arch/arm/isa/templates/basic.isa
@@ -49,7 +49,7 @@ def template BasicDeclare {{
 
 // Basic instruction class constructor template.
 def template BasicConstructor {{
-        inline %(class_name)s::%(class_name)s(ExtMachInst machInst)  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+        %(class_name)s::%(class_name)s(ExtMachInst machInst)  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
         {
                 %(constructor)s;
                 if (!(condCode == COND_AL || condCode == COND_UC)) {
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index db097c653..c31818377 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -411,7 +411,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
         }
         break;
       case 11:
-        if (opc1 >= 0 && opc1 <=7) {
+        if (opc1 <=7) {
             switch (crm) {
               case 0:
               case 1:
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index b2ab010c0..9c92ebdf6 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -107,8 +107,9 @@ TableWalker::getPort(const std::string &if_name, int idx)
 
 Fault
 TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode,
-            TLB::Translation *_trans, bool _timing)
+            TLB::Translation *_trans, bool _timing, bool _functional)
 {
+    assert(!(_functional && _timing));
     if (!currState) {
         // For atomic mode, a new WalkerState instance should be only created
         // once per TLB. For timing mode, a new instance is generated for every
@@ -136,6 +137,7 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _
     currState->fault = NoFault;
     currState->contextId = _cid;
     currState->timing = _timing;
+    currState->functional = _functional;
     currState->mode = _mode;
 
     /** @todo These should be cached or grabbed from cached copies in
@@ -230,12 +232,21 @@ TableWalker::processWalk()
                 stateQueueL1.size());
         stateQueueL1.push_back(currState);
         currState = NULL;
-    } else {
+    } else if (!currState->functional) {
         port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
                 NULL, (uint8_t*)&currState->l1Desc.data,
                 currState->tc->getCpuPtr()->ticks(1), flag);
         doL1Descriptor();
         f = currState->fault;
+    } else {
+        RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag);
+        PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+        pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
+        port->sendFunctional(pkt);
+        doL1Descriptor();
+        delete req;
+        delete pkt;
+        f = currState->fault;
     }
 
     return f;
@@ -566,11 +577,19 @@ TableWalker::doL1Descriptor()
             port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
                     &doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
                     currState->tc->getCpuPtr()->ticks(1));
-        } else {
+        } else if (!currState->functional) {
             port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
                     NULL, (uint8_t*)&currState->l2Desc.data,
                     currState->tc->getCpuPtr()->ticks(1));
             doL2Descriptor();
+        } else {
+            RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0);
+            PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+            pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
+            port->sendFunctional(pkt);
+            doL2Descriptor();
+            delete req;
+            delete pkt;
         }
         return;
       default:
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 85db1fa77..d4a2e87b5 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -294,6 +294,9 @@ class TableWalker : public MemObject
         /** If the mode is timing or atomic */
         bool timing;
 
+        /** If the atomic mode should be functional */
+        bool functional;
+
         /** Save mode for use in delayed response */
         BaseTLB::Mode mode;
 
@@ -354,7 +357,7 @@ class TableWalker : public MemObject
     virtual Port *getPort(const std::string &if_name, int idx = -1);
 
     Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
-            TLB::Translation *_trans, bool timing);
+            TLB::Translation *_trans, bool timing, bool functional = false);
 
     void setTlb(TLB *_tlb) { tlb = _tlb; }
     void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index b19ad5265..0b003e9fb 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -443,8 +443,11 @@ TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
 
 Fault
 TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
-        Translation *translation, bool &delay, bool timing)
+        Translation *translation, bool &delay, bool timing, bool functional)
 {
+    // No such thing as a functional timing access
+    assert(!(timing && functional));
+
     if (!miscRegValid) {
         updateMiscReg(tc);
         DPRINTF(TLBVerbose, "TLB variables changed!\n");
@@ -531,7 +534,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
         DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
                 vaddr, contextId);
         fault = tableWalker->walk(req, tc, contextId, mode, translation,
-                timing);
+                                  timing, functional);
         if (timing && fault == NoFault) {
             delay = true;
             // for timing mode, return and wait for table walk
@@ -687,6 +690,19 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 }
 
 Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+    bool delay = false;
+    Fault fault;
+    if (FullSystem)
+        fault = translateFs(req, tc, mode, NULL, delay, false, true);
+    else
+        fault = translateSe(req, tc, mode, NULL, delay, false);
+    assert(!delay);
+    return fault;
+}
+
+Fault
 TLB::translateTiming(RequestPtr req, ThreadContext *tc,
         Translation *translation, Mode mode)
 {
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 0bf13fe83..daf59f01d 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -180,6 +180,12 @@ class TLB : public BaseTLB
      */
     bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
 
+    /**
+     * Do a functional lookup on the TLB (for checker cpu) that
+     * behaves like a normal lookup without modifying any page table state.
+     */
+    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+
     /** Accessor functions for memory attributes for last accessed TLB entry
      */
     void
@@ -194,7 +200,8 @@ class TLB : public BaseTLB
     }
 
     Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
-            Translation *translation, bool &delay, bool timing);
+            Translation *translation, bool &delay,
+            bool timing, bool functional = false);
     Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
             Translation *translation, bool &delay, bool timing);
     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index ac81c7db6..0527e135f 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -43,6 +43,7 @@
 #include "arch/arm/tlb.hh"
 #include "arch/arm/utility.hh"
 #include "arch/arm/vtophys.hh"
+#include "config/use_checker.hh"
 #include "cpu/thread_context.hh"
 #include "mem/fs_translating_port_proxy.hh"
 #include "sim/full_system.hh"
@@ -113,7 +114,11 @@ skipFunction(ThreadContext *tc)
 {
     TheISA::PCState newPC = tc->pcState();
     newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
+#if USE_CHECKER
+    tc->pcStateNoRecord(newPC);
+#else
     tc->pcState(newPC);
+#endif
 }
 
 void
diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh
index c753aaf2a..f7bbfa269 100644
--- a/src/arch/generic/memhelpers.hh
+++ b/src/arch/generic/memhelpers.hh
@@ -64,7 +64,7 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
     memset(&mem, 0, sizeof(mem));
     Fault fault = readMemTiming(xc, traceData, addr, mem, flags);
     if (fault == NoFault) {
-        mem = gtoh(mem);
+        mem = TheISA::gtoh(mem);
         if (traceData)
             traceData->setData(mem);
     }
@@ -92,7 +92,7 @@ writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
 {
     Fault fault = writeMemTiming(xc, traceData, mem, addr, flags, res);
     if (fault == NoFault && res != NULL) {
-        *res = gtoh((MemT)*res);
+        *res = TheISA::gtoh((MemT)*res);
     }
     return fault;
 }
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 3076e0afe..3697601dc 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -95,7 +95,7 @@ template <> FaultVals MipsFault<TlbInvalidFault>::vals =
 template <> FaultVals MipsFault<TlbRefillFault>::vals =
     { "TLB Refill Exception", 0x180, ExcCodeDummy };
 
-template <> FaultVals MipsFault<TlbModifiedFault>::vals =
+template <> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals =
     { "TLB Modified Exception", 0x180, ExcCodeMod };
 
 void
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index b90c38e99..98638ac9a 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -300,7 +300,7 @@ class TlbModifiedFault : public TlbFault<TlbModifiedFault>
         TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false)
     {}
 
-    ExcCode code() const { return vals.code; }
+    ExcCode code() const { return MipsFault<TlbModifiedFault>::code(); }
 };
 
 } // namespace MipsISA
diff --git a/src/arch/x86/bios/acpi.hh b/src/arch/x86/bios/acpi.hh
index 5040c434c..b10b18092 100644
--- a/src/arch/x86/bios/acpi.hh
+++ b/src/arch/x86/bios/acpi.hh
@@ -48,11 +48,11 @@
 
 class Port;
 
-class X86ACPIRSDPParams;
+struct X86ACPIRSDPParams;
 
-class X86ACPISysDescTableParams;
-class X86ACPIRSDTParams;
-class X86ACPIXSDTParams;
+struct X86ACPISysDescTableParams;
+struct X86ACPIRSDTParams;
+struct X86ACPIXSDTParams;
 
 namespace X86ISA
 {
diff --git a/src/arch/x86/bios/intelmp.cc b/src/arch/x86/bios/intelmp.cc
index 974af28a5..4c9c61adb 100644
--- a/src/arch/x86/bios/intelmp.cc
+++ b/src/arch/x86/bios/intelmp.cc
@@ -72,7 +72,7 @@ template<class T>
 uint8_t
 writeOutField(PortProxy* proxy, Addr addr, T val)
 {
-    T guestVal = X86ISA::htog(val);
+    uint64_t guestVal = X86ISA::htog(val);
     proxy->writeBlob(addr, (uint8_t *)(&guestVal), sizeof(T));
 
     uint8_t checkSum = 0;
diff --git a/src/arch/x86/bios/intelmp.hh b/src/arch/x86/bios/intelmp.hh
index 0ddb62b8d..4b730ad4b 100644
--- a/src/arch/x86/bios/intelmp.hh
+++ b/src/arch/x86/bios/intelmp.hh
@@ -54,24 +54,24 @@
 class PortProxy;
 
 // Config entry types
-class X86IntelMPBaseConfigEntryParams;
-class X86IntelMPExtConfigEntryParams;
+struct X86IntelMPBaseConfigEntryParams;
+struct X86IntelMPExtConfigEntryParams;
 
 // General table structures
-class X86IntelMPConfigTableParams;
-class X86IntelMPFloatingPointerParams;
+struct X86IntelMPConfigTableParams;
+struct X86IntelMPFloatingPointerParams;
 
 // Base entry types
-class X86IntelMPBusParams;
-class X86IntelMPIOAPICParams;
-class X86IntelMPIOIntAssignmentParams;
-class X86IntelMPLocalIntAssignmentParams;
-class X86IntelMPProcessorParams;
+struct X86IntelMPBusParams;
+struct X86IntelMPIOAPICParams;
+struct X86IntelMPIOIntAssignmentParams;
+struct X86IntelMPLocalIntAssignmentParams;
+struct X86IntelMPProcessorParams;
 
 // Extended entry types
-class X86IntelMPAddrSpaceMappingParams;
-class X86IntelMPBusHierarchyParams;
-class X86IntelMPCompatAddrSpaceModParams;
+struct X86IntelMPAddrSpaceMappingParams;
+struct X86IntelMPBusHierarchyParams;
+struct X86IntelMPCompatAddrSpaceModParams;
 
 namespace X86ISA
 {
diff --git a/src/arch/x86/bios/smbios.hh b/src/arch/x86/bios/smbios.hh
index 9fa6cd6dc..805b03fbb 100644
--- a/src/arch/x86/bios/smbios.hh
+++ b/src/arch/x86/bios/smbios.hh
@@ -52,9 +52,9 @@
 #include "sim/sim_object.hh"
 
 class PortProxy;
-class X86SMBiosBiosInformationParams;
-class X86SMBiosSMBiosStructureParams;
-class X86SMBiosSMBiosTableParams;
+struct X86SMBiosBiosInformationParams;
+struct X86SMBiosSMBiosStructureParams;
+struct X86SMBiosSMBiosTableParams;
 
 namespace X86ISA
 {