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| author | Gabe Black <gabeblack@google.com> | 2019-11-04 16:27:34 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-11-26 03:01:32 +0000 |
| commit | 57e951f6eae1de88988a9b13035c07985a0bcd73 (patch) | |
| tree | e0eebcc48ab14e7106f1a41b09d82f8390357c34 /src/arch | |
| parent | 97a6a64f286fb07557843d88776fbc69606b9d88 (diff) | |
| download | gem5-57e951f6eae1de88988a9b13035c07985a0bcd73.tar.xz | |
arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs.
This conditional compilation was unnecessary and makes gem5 more
brittle and harder to understand.
Change-Id: I63abaf2668252c988cdd4626ff6a462eb6f54b04
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22544
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/registers.hh | 2 | ||||
| -rw-r--r-- | src/arch/x86/registers.hh | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index a97a4ce25..84f382b9c 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -102,8 +102,6 @@ const int INTRLVREG1 = INTRLVREG0 + 1; const int INTRLVREG2 = INTRLVREG0 + 2; const int INTRLVREG3 = INTRLVREG0 + 3; -#define ISA_HAS_CC_REGS - const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + NumVecPredRegs + NumMiscRegs; diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh index 0590abe49..479eda118 100644 --- a/src/arch/x86/registers.hh +++ b/src/arch/x86/registers.hh @@ -60,8 +60,6 @@ const int NumIntArchRegs = NUM_INTREGS; const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs; const int NumCCRegs = NUM_CCREGS; -#define ISA_HAS_CC_REGS - // Each 128 bit xmm register is broken into two effective 64 bit registers. // Add 8 for the indices that are mapped over the fp stack const int NumFloatRegs = |